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352 linus 5560d 10h /plasma/tags/V3_0/vhdl/
350 root 5589d 05h /plasma/tags/V3_0/vhdl/
140 This commit was manufactured by cvs2svn to create tag 'V3_0'. 6689d 17h /plasma/tags/V3_0/vhdl/
139 Major changes -- updated to Plasma Version 3 rhoads 6689d 17h /plasma/tags/V3_0/vhdl/
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7169d 16h /plasma/tags/V3_0/vhdl/
131 Changed "GENERIC" to "DEFAULT" to be Xilinx friendly. rhoads 7169d 16h /plasma/tags/V3_0/vhdl/
129 Added reset_in to sensitivity list rhoads 7188d 16h /plasma/tags/V3_0/vhdl/
128 Reset all registers, constants now upper case. rhoads 7307d 03h /plasma/tags/V3_0/vhdl/
125 Fixed pc_source_type comment. rhoads 7325d 17h /plasma/tags/V3_0/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7325d 17h /plasma/tags/V3_0/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7392d 17h /plasma/tags/V3_0/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7456d 18h /plasma/tags/V3_0/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7468d 06h /plasma/tags/V3_0/vhdl/
120 Make generics "GENERIC" rhoads 7468d 06h /plasma/tags/V3_0/vhdl/
119 Opcodes from count.c rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7506d 17h /plasma/tags/V3_0/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7780d 14h /plasma/tags/V3_0/vhdl/
107 merged rising_edge(clk) statements rhoads 7780d 14h /plasma/tags/V3_0/vhdl/
106 better test mem_pause rhoads 7783d 16h /plasma/tags/V3_0/vhdl/
105 better test mem_pause rhoads 7783d 16h /plasma/tags/V3_0/vhdl/
103 shorten similation times rhoads 7784d 15h /plasma/tags/V3_0/vhdl/
102 permit testing mem_pause rhoads 7784d 15h /plasma/tags/V3_0/vhdl/
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7784d 15h /plasma/tags/V3_0/vhdl/
99 correct upper 32-bits for mult(-1,-1) rhoads 7926d 15h /plasma/tags/V3_0/vhdl/

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