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Rev Log message Author Age Path
54 Update benchmarks to work with supervisor spec v1.7 skordal 3260d 08h /potato/
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3262d 08h /potato/
52 Correct .data section of sw-jal test skordal 3262d 08h /potato/
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3262d 09h /potato/
50 Update test environment to the new supervisor ISA skordal 3274d 09h /potato/
49 Correct spelling of "privileged" skordal 3284d 08h /potato/
48 Create branch for upgrading to the new privileged ISA skordal 3284d 08h /potato/
47 Tag version 0.1 of the Potato Processor skordal 3284d 16h /potato/
46 Remove branch: cache-playground skordal 3287d 10h /potato/
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.		 skordal 3287d 10h /potato/
44 Add instruction cache and use the WB adapter as dmem interface skordal 3287d 10h /potato/
43 Improve instruction fetch logic skordal 3287d 10h /potato/
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3287d 10h /potato/
41 Make continouous status register reads asynchronous skordal 3287d 10h /potato/
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3287d 10h /potato/
39 Disable IRQs when handling exceptions skordal 3287d 11h /potato/
38 Add "Hello World" test application skordal 3287d 12h /potato/
37 Add macro to set the TOHOST register from C code skordal 3287d 12h /potato/
36 Ensure correct read of CSR after stall skordal 3287d 12h /potato/
35 Prevent jumping/branching when stalling skordal 3287d 12h /potato/
34 Prevent flushing the pipeline if it is stalling skordal 3287d 12h /potato/
33 Ensure correct read of CSR after stall skordal 3287d 12h /potato/
32 Prevent jumping/branching when stalling skordal 3290d 09h /potato/
31 Prevent flushing the pipeline if it is stalling skordal 3290d 10h /potato/
30 Add testcase for a combination of instructions that fail when using cache skordal 3292d 15h /potato/
29 Add reset functionality for the WB arbiter state machine skordal 3295d 10h /potato/
28 Add rudimentary User's manual skordal 3301d 09h /potato/
27 Prevent exceptions from being taken while stalling skordal 3301d 11h /potato/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.		 skordal 3301d 14h /potato/
25 Add placeholder cache modules and a wishbone arbiter skordal 3303d 19h /potato/

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