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[/] [potato/] [trunk/] - Rev 65

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65 Update platform headers and add cache control commands

Cache control is currently no-ops on Potato.		 skordal 3203d 08h /potato/trunk/
64 Add display enable support for the 7-seg module skordal 3203d 08h /potato/trunk/
63 Upgrade makefiles for use with the upgraded toolchain skordal 3206d 08h /potato/trunk/
62 Add a couple of missing signals to a sensitivity list skordal 3234d 09h /potato/trunk/
61 Add 7-segment display controller to the Potato SoC skordal 3235d 12h /potato/trunk/
60 Remove out-of-date comment skordal 3249d 05h /potato/trunk/
58 Merge branch new-privileged-isa (r48-r57) into trunk

This adds support for the newly published supervisor extensions
version 1.7. In addition, a processor datasheet has been added
and the timer_clk signal has been properly connected in the
example design and the SoC testbench.		 skordal 3269d 09h /potato/trunk/
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.		 skordal 3301d 04h /potato/trunk/
36 Ensure correct read of CSR after stall skordal 3301d 05h /potato/trunk/
35 Prevent jumping/branching when stalling skordal 3301d 05h /potato/trunk/
34 Prevent flushing the pipeline if it is stalling skordal 3301d 05h /potato/trunk/
28 Add rudimentary User's manual skordal 3315d 03h /potato/trunk/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.		 skordal 3315d 08h /potato/trunk/
24 Remove unused STRINGIFY macros skordal 3318d 01h /potato/trunk/
22 Fix the potato_get_badvaddr() macro skordal 3318d 02h /potato/trunk/
21 Upgrade the example design to use a 60 MHz system clock skordal 3318d 02h /potato/trunk/
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.		 skordal 3318d 02h /potato/trunk/
19 SHA256 benchmark: allow compiler to inline at will skordal 3318d 02h /potato/trunk/
18 instr_misalign_check: add do_jump to sensitivity list skordal 3320d 02h /potato/trunk/
17 Improve detection of unaligned instructions skordal 3324d 09h /potato/trunk/
16 Correct grammar in source code comment skordal 3324d 09h /potato/trunk/
15 SHA256 benchmark: fix Makefile syntax error skordal 3331d 02h /potato/trunk/
14 Improve detection of invalid instructions skordal 3331d 03h /potato/trunk/
13 Add SHA256 benchmark code skordal 3331d 07h /potato/trunk/
12 Update example design with correct bug-report URL and testbenches skordal 3331d 09h /potato/trunk/
11 Correct FIFO file header skordal 3331d 10h /potato/trunk/
10 Add missing FIFO module skordal 3336d 04h /potato/trunk/
9 Remove dependency on a non-existent target in the Makefile skordal 3336d 04h /potato/trunk/
8 Clarify instruction ROM naming in the example design README skordal 3343d 06h /potato/trunk/
7 Add test design for the Nexys 4 board from Digilent skordal 3343d 06h /potato/trunk/

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