Rev |
Log message |
Author |
Age |
Path |
219 |
RayTrac: Non tested and witouh TSE |
jguarin2002 |
4386d 14h |
/raytrac/ |
218 |
Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : SOPC Library TCL scrip, load it into the Altera Project |
jguarin2002 |
4386d 18h |
/raytrac/ |
217 |
Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used |
jguarin2002 |
4386d 18h |
/raytrac/ |
216 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4387d 09h |
/raytrac/ |
215 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4387d 09h |
/raytrac/ |
214 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4387d 09h |
/raytrac/ |
213 |
Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) |
jguarin2002 |
4387d 09h |
/raytrac/ |
212 |
DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. |
jguarin2002 |
4387d 09h |
/raytrac/ |
211 |
Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! |
jguarin2002 |
4387d 10h |
/raytrac/ |
210 |
Document advance..... towards dma oriented raytrac |
jguarin2002 |
4398d 22h |
/raytrac/ |
209 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
208 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
207 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
206 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
205 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
204 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
203 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
202 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4398d 22h |
/raytrac/ |
201 |
files no longer needed im.vhd and fadd32long.vhd |
jguarin2002 |
4398d 23h |
/raytrac/ |
200 |
raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers |
jguarin2002 |
4398d 23h |
/raytrac/ |
199 |
Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work |
jguarin2002 |
4415d 05h |
/raytrac/ |
198 |
Check out for the best out for the best organization so the datapath does not consume to many logic cells |
jguarin2002 |
4415d 05h |
/raytrac/ |
197 |
Chnages on interconnectivity: Check out the SGDMA Sheets |
jguarin2002 |
4425d 06h |
/raytrac/ |
196 |
raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues |
jguarin2002 |
4428d 17h |
/raytrac/ |
195 |
Document advance and changes in the design |
jguarin2002 |
4431d 14h |
/raytrac/ |
194 |
Work In Progress |
jguarin2002 |
4446d 20h |
/raytrac/ |
193 |
WIP: Main Document |
jguarin2002 |
4447d 17h |
/raytrac/ |
192 |
Some change I dont realize what is it in the design document (xls) |
jguarin2002 |
4448d 04h |
/raytrac/ |
191 |
Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. |
jguarin2002 |
4448d 04h |
/raytrac/ |
190 |
M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... |
jguarin2002 |
4452d 13h |
/raytrac/ |