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[/] [rise/] [trunk/] [vhdl/] - Rev 101

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Rev	Log message	Author	Age	Path
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6376d 18h	/rise/trunk/vhdl/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6376d 18h	/rise/trunk/vhdl/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6376d 18h	/rise/trunk/vhdl/
98	- Applied indenting tool.	cwalter	6376d 18h	/rise/trunk/vhdl/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6376d 19h	/rise/trunk/vhdl/
96	- SR register is now computed in ALU stage.	cwalter	6376d 19h	/rise/trunk/vhdl/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6376d 19h	/rise/trunk/vhdl/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6376d 20h	/rise/trunk/vhdl/
93	Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result.	jlechner	6376d 20h	/rise/trunk/vhdl/
92	Added logic for inserting a nop instruction when the pipeline is cleared.	jlechner	6376d 20h	/rise/trunk/vhdl/
91	- Computed new SR values from ALU result.	cwalter	6376d 20h	/rise/trunk/vhdl/
90	Added output signal for clearing all register locks when a branch instruction is executed. This is necessary because the id stage could have locked registers for an instruction that is cleared out of the pipeline due to the branch.	jlechner	6376d 20h	/rise/trunk/vhdl/
89	Added input signal for clearing all register locks.	jlechner	6376d 20h	/rise/trunk/vhdl/
86	- Added new example for a more complex loop.	cwalter	6376d 21h	/rise/trunk/vhdl/
85	Removed PC reset on clear_in signal. Clear_in only comes together with a branch, so it is sufficient branch immediately.	jlechner	6376d 23h	/rise/trunk/vhdl/
84	- PC value was wrong.	cwalter	6376d 23h	/rise/trunk/vhdl/
83	- sr_enable and lr_enable where incorrect.	cwalter	6376d 23h	/rise/trunk/vhdl/
80	- Fixed testbench to work with new barrel shifter.	cwalter	6376d 23h	/rise/trunk/vhdl/
79	- Added barrel shifter.	cwalter	6376d 23h	/rise/trunk/vhdl/
78	Added stall_in to sensitivity list.	jlechner	6376d 23h	/rise/trunk/vhdl/
77	- Fixed case.	cwalter	6376d 23h	/rise/trunk/vhdl/
76	- Changed order of some statements to improve readability.	cwalter	6376d 23h	/rise/trunk/vhdl/
75	- Added barrel shifter implementation.	cwalter	6377d 00h	/rise/trunk/vhdl/
74	- Fixed bug where register value used by load was passed through to write back. Correct is ALU value.	cwalter	6377d 01h	/rise/trunk/vhdl/
73	- Fixed bug where immediate value for LD_IMM_HB was placed in the upper 8bits. This is done by the execute stage.	cwalter	6377d 01h	/rise/trunk/vhdl/
72	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation Added call to conversion function where a std_logic_vector is assigned to a opcode signal or a condition signal.	jlechner	6377d 11h	/rise/trunk/vhdl/
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6377d 11h	/rise/trunk/vhdl/
70	Moved opcode and conditional constants and opcode_t and cond_t data types to rise_const_pack.vhd.	jlechner	6377d 11h	/rise/trunk/vhdl/
69	Synthesis package containing opcode and conditional constants used in other vhd files. Package also contains convert functions from std_logic_vector to the appropriate data type.	jlechner	6377d 11h	/rise/trunk/vhdl/
68	Simulation package containing enumeration types for opcodes and condition codes. Package also contains convert functions from std_logic_vector to the appropriate enumeration type.	jlechner	6377d 11h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 101

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