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[/] [rise/] [trunk/] [vhdl/] - Rev 126

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Rev	Log message	Author	Age	Path
126	Added constant for cpu frequency (needed for UART)	trinklhar	6405d 03h	/rise/trunk/vhdl/
125	Fixed vhdl bugs	trinklhar	6405d 03h	/rise/trunk/vhdl/
124	Assigned UART signals to ports on top-level entity	trinklhar	6405d 03h	/rise/trunk/vhdl/
123	Removed UART again	trinklhar	6405d 04h	/rise/trunk/vhdl/
122	Removed UART again again	trinklhar	6405d 04h	/rise/trunk/vhdl/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6405d 04h	/rise/trunk/vhdl/
120	Added UART module to memory entity	trinklhar	6405d 04h	/rise/trunk/vhdl/
119	Uart wieder ausgebaut	trinklhar	6405d 23h	/rise/trunk/vhdl/
118	insert Uart address constant	trinklhar	6405d 23h	/rise/trunk/vhdl/
117	Uart im mem_stage	trinklhar	6405d 23h	/rise/trunk/vhdl/
116	writes to uart when write to reg 0	trinklhar	6407d 05h	/rise/trunk/vhdl/
115	* empty log message *	trinklhar	6407d 19h	/rise/trunk/vhdl/
114	Uart 0.3	trinklhar	6408d 23h	/rise/trunk/vhdl/
113	Uart reset funkt	trinklhar	6409d 00h	/rise/trunk/vhdl/
112	Uart drin aber signale nicht eingebunden	trinklhar	6409d 02h	/rise/trunk/vhdl/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6411d 17h	/rise/trunk/vhdl/
110	- Added missing file to CVS.	cwalter	6412d 00h	/rise/trunk/vhdl/
107	- Added new example for memory testing.	cwalter	6412d 16h	/rise/trunk/vhdl/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6412d 16h	/rise/trunk/vhdl/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6412d 16h	/rise/trunk/vhdl/
104	- Added missing signal dmem_data_in.	cwalter	6412d 17h	/rise/trunk/vhdl/
102	changed data pitch	ustadler	6414d 22h	/rise/trunk/vhdl/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6414d 22h	/rise/trunk/vhdl/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6414d 22h	/rise/trunk/vhdl/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6414d 22h	/rise/trunk/vhdl/
98	- Applied indenting tool.	cwalter	6414d 22h	/rise/trunk/vhdl/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6414d 23h	/rise/trunk/vhdl/
96	- SR register is now computed in ALU stage.	cwalter	6414d 23h	/rise/trunk/vhdl/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6415d 00h	/rise/trunk/vhdl/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6415d 00h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 126

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