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[/] [rise/] [trunk/] [vhdl/] - Rev 135

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Rev Log message Author Age Path
135 uart_address_0 was a latch -> changed ustadler 6404d 14h /rise/trunk/vhdl/
134 Added second test program for testing uart. jlechner 6404d 14h /rise/trunk/vhdl/
132 Added test program for testing uart. jlechner 6404d 16h /rise/trunk/vhdl/
131 Changed high active resets to low active ones. jlechner 6404d 16h /rise/trunk/vhdl/
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6404d 16h /rise/trunk/vhdl/
127 Changed high active resets to low active ones. jlechner 6404d 16h /rise/trunk/vhdl/
126 Added constant for cpu frequency (needed for UART) trinklhar 6404d 23h /rise/trunk/vhdl/
125 Fixed vhdl bugs trinklhar 6404d 23h /rise/trunk/vhdl/
124 Assigned UART signals to ports on top-level entity trinklhar 6404d 23h /rise/trunk/vhdl/
123 Removed UART again trinklhar 6405d 00h /rise/trunk/vhdl/
122 Removed UART again again trinklhar 6405d 00h /rise/trunk/vhdl/
121 Added address constants for uart access (memory mapped I/O) trinklhar 6405d 00h /rise/trunk/vhdl/
120 Added UART module to memory entity trinklhar 6405d 00h /rise/trunk/vhdl/
119 Uart wieder ausgebaut trinklhar 6405d 19h /rise/trunk/vhdl/
118 insert Uart address constant trinklhar 6405d 19h /rise/trunk/vhdl/
117 Uart im mem_stage trinklhar 6405d 19h /rise/trunk/vhdl/
116 writes to uart when write to reg 0 trinklhar 6407d 01h /rise/trunk/vhdl/
115 *** empty log message *** trinklhar 6407d 15h /rise/trunk/vhdl/
114 Uart 0.3 trinklhar 6408d 19h /rise/trunk/vhdl/
113 Uart reset funkt trinklhar 6408d 20h /rise/trunk/vhdl/
112 Uart drin aber signale nicht eingebunden trinklhar 6408d 22h /rise/trunk/vhdl/
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6411d 14h /rise/trunk/vhdl/
110 - Added missing file to CVS. cwalter 6411d 20h /rise/trunk/vhdl/
107 - Added new example for memory testing. cwalter 6412d 12h /rise/trunk/vhdl/
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6412d 12h /rise/trunk/vhdl/
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6412d 12h /rise/trunk/vhdl/
104 - Added missing signal dmem_data_in. cwalter 6412d 13h /rise/trunk/vhdl/
102 changed data pitch ustadler 6414d 18h /rise/trunk/vhdl/
101 - Signals for memory block where not always set. This resulted in a latch. cwalter 6414d 18h /rise/trunk/vhdl/
100 - Signal clear_in was missing in sensitivity list. cwalter 6414d 18h /rise/trunk/vhdl/

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