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[/] [rise/] [trunk/] [vhdl/] - Rev 40

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Rev	Log message	Author	Age	Path
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6389d 20h	/rise/trunk/vhdl/
39	- Added wr_enable signals for imem and dmem - Changed signals for register lock unit (this concerns id-stage and write-back-stage)	jlechner	6389d 20h	/rise/trunk/vhdl/
38	Memory output signal is now passed on asynchronously to write back stage.	jlechner	6389d 20h	/rise/trunk/vhdl/
37	Applied VHDL indent.	jlechner	6389d 20h	/rise/trunk/vhdl/
36	- Testbench for RISE.	cwalter	6389d 20h	/rise/trunk/vhdl/
35	- Testbench for register file.	cwalter	6389d 20h	/rise/trunk/vhdl/
34	- Filex have been renamed to have tb prefix.	cwalter	6389d 20h	/rise/trunk/vhdl/
33	- Fixed process sensitivity list.	cwalter	6389d 21h	/rise/trunk/vhdl/
32	- When this stage asserts stall_out it must clear the input for the next stage. - Fixed process sensitivity list.	cwalter	6389d 21h	/rise/trunk/vhdl/
31	- Added PC_RESET_VECTOR constant.	cwalter	6389d 22h	/rise/trunk/vhdl/
30	- Top level testbench for RISE.	cwalter	6389d 22h	/rise/trunk/vhdl/
29	- Initial version of IF stage with dummy instructions.	cwalter	6389d 23h	/rise/trunk/vhdl/
28	Added new register write enable signals.	jlechner	6391d 16h	/rise/trunk/vhdl/
27	Added new register write enable signals to component instantiation of register_file and wb_stage.	jlechner	6391d 16h	/rise/trunk/vhdl/
26	Applied VHDL indent.	jlechner	6391d 16h	/rise/trunk/vhdl/
25	netlist file for the memories is needed for IMEM and DMEM	ustadler	6392d 16h	/rise/trunk/vhdl/
24	4k Data Instruction for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6392d 16h	/rise/trunk/vhdl/
23	4k Data Memory for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6392d 16h	/rise/trunk/vhdl/
22	testbench für die register file	ustadler	6393d 06h	/rise/trunk/vhdl/
21	überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt	ustadler	6393d 17h	/rise/trunk/vhdl/
20	- Fixed bug where SR fetch code locked wrong register.	cwalter	6393d 19h	/rise/trunk/vhdl/
19	Version 1.2 der register file	ustadler	6394d 03h	/rise/trunk/vhdl/
17	- Added new tests for pipeline stall signal. - Added tests for register locking. - Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.	cwalter	6396d 19h	/rise/trunk/vhdl/
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6396d 19h	/rise/trunk/vhdl/
15	- Added second register locking port reg_lock1. - Added function to check if the instruction modifies the SR register. - Fetch of SR now checks if the SR is modified and if yes the SR register is marked as locked. - Stall signal for pipeline is now generated correctly. - Stall input is now checked. If asserted the current output values are hold until the stall signal is deasserted.	cwalter	6396d 19h	/rise/trunk/vhdl/
14	- Renamed clear/set_reg_lock to clear/set_reg_lock0. - Added second register locking port reg_lock1.	cwalter	6396d 19h	/rise/trunk/vhdl/
13	- Testbench now implements a simple register file. - Added new tests for OPCODE_LD_DISP, OPCODE_LD_DISP_MS OPCODE_LD_REG.	cwalter	6399d 17h	/rise/trunk/vhdl/
12	- Added constant definitions for SR, PC and LR register.	cwalter	6399d 17h	/rise/trunk/vhdl/
11	- Added checks to test if a register has been locked. If it is locked and used in the decoded instruction the stall_out signal is asserted. - Added missing signals to process sensitivity list. - Fixed bug in rY decoding where the value of rZ was used. - Implemented opcode_modifies_rx.	cwalter	6399d 17h	/rise/trunk/vhdl/
10	- added testbench for load immediate and load immediate with high byte.	cwalter	6401d 21h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 40

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