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[/] [rise/] [trunk/] [vhdl/] - Rev 74

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Rev	Log message	Author	Age	Path
74	- Fixed bug where register value used by load was passed through to write back. Correct is ALU value.	cwalter	6424d 08h	/rise/trunk/vhdl/
73	- Fixed bug where immediate value for LD_IMM_HB was placed in the upper 8bits. This is done by the execute stage.	cwalter	6424d 08h	/rise/trunk/vhdl/
72	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation Added call to conversion function where a std_logic_vector is assigned to a opcode signal or a condition signal.	jlechner	6424d 17h	/rise/trunk/vhdl/
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6424d 17h	/rise/trunk/vhdl/
70	Moved opcode and conditional constants and opcode_t and cond_t data types to rise_const_pack.vhd.	jlechner	6424d 17h	/rise/trunk/vhdl/
69	Synthesis package containing opcode and conditional constants used in other vhd files. Package also contains convert functions from std_logic_vector to the appropriate data type.	jlechner	6424d 17h	/rise/trunk/vhdl/
68	Simulation package containing enumeration types for opcodes and condition codes. Package also contains convert functions from std_logic_vector to the appropriate enumeration type.	jlechner	6424d 17h	/rise/trunk/vhdl/
66	Moved constants for opcode and conditionals in seperate package.	jlechner	6424d 17h	/rise/trunk/vhdl/
63	- Added missing signal stall_out_int to sensitivity list. - LR register now locked if opcode is JUMP.	cwalter	6424d 19h	/rise/trunk/vhdl/
61	- Applied indenting tool. - Added first basic implementation for testing.	cwalter	6424d 21h	/rise/trunk/vhdl/
60	- Applied indenting tool.	cwalter	6424d 21h	/rise/trunk/vhdl/
59	- We don't want to lock registers the next cycle when we have stalled the previous stages. - Load opcodes also need to lock registers.	cwalter	6424d 21h	/rise/trunk/vhdl/
58	- lr_enable signal in component wb_state should have direction out.	cwalter	6424d 22h	/rise/trunk/vhdl/
57	- applied indenting tool.	cwalter	6424d 23h	/rise/trunk/vhdl/
56	new sensitivity list	ustadler	6424d 23h	/rise/trunk/vhdl/
55	- clear_out must be initialized to '0'.	cwalter	6425d 00h	/rise/trunk/vhdl/
54	- Changed reset delay.	cwalter	6425d 00h	/rise/trunk/vhdl/
53	- Removed unused constant COND_NONE.	cwalter	6425d 00h	/rise/trunk/vhdl/
52	- stall_out must be initialized to '0'	cwalter	6425d 00h	/rise/trunk/vhdl/
51	- stall_out logic has moved to synchronous process.	cwalter	6425d 00h	/rise/trunk/vhdl/
50	- Added assembler example. - Added logic for stall_in. pc_next must not be updated on stall.	cwalter	6425d 00h	/rise/trunk/vhdl/
49	data can be ead asynchronous, data is written with the rising edge of the clk	ustadler	6425d 01h	/rise/trunk/vhdl/
46	- Added constant for RESET_VECTOR.	cwalter	6425d 05h	/rise/trunk/vhdl/
45	- Fixed latch for pc_next.	cwalter	6425d 21h	/rise/trunk/vhdl/
44	- Added another version of a register file which is a bit simplier.	cwalter	6425d 21h	/rise/trunk/vhdl/
43	Correct implementation of necessary unlocking signals that are conncted to register locking unit.	jlechner	6425d 21h	/rise/trunk/vhdl/
42	Modified input signals for register locking (testbench modifications): Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6425d 21h	/rise/trunk/vhdl/
41	Modified input signals for register locking: Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6425d 21h	/rise/trunk/vhdl/
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6425d 21h	/rise/trunk/vhdl/
39	- Added wr_enable signals for imem and dmem - Changed signals for register lock unit (this concerns id-stage and write-back-stage)	jlechner	6425d 21h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 74

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