OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] - Rev 37

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
37 - latest documentation robfinch 3896d 19h /rtf65002/
36 - missing TRB/TSB instructions in 32 bit mode added robfinch 3896d 19h /rtf65002/
35 - several bug fixes
- mul,mod,div immediates mode than 8 bits
- page two opcode fix on cache miss
- setting upper pc bits in emulation mode (store)		 robfinch 3943d 12h /rtf65002/
34 - latest bootrom.asm
- and assembler		 robfinch 3954d 02h /rtf65002/
33 - most recent docs robfinch 3954d 02h /rtf65002/
32 - many changes
- new instructions
- code reorganization		 robfinch 3954d 02h /rtf65002/
31 - miscellaneous updates
- unimplemented instruction vector
-		 robfinch 3964d 00h /rtf65002/
30 - added additional branches
- modified the pc increment
- modified interrupts, all vector through BRK
- registered some decodes
- added SUPPORT macros to allow core trimming		 robfinch 3964d 00h /rtf65002/
29 - updated assembler, increased instruction support robfinch 3969d 19h /rtf65002/
28 - updated bootrom, robfinch 3969d 19h /rtf65002/
27 - most recent doc robfinch 3971d 02h /rtf65002/
26 - latest bootrom.asm
- fixes to assembler		 robfinch 3971d 02h /rtf65002/
25 - add EXEC and ATNI instructions
- fix store byte zero page indexed
- fix break instruction		 robfinch 3971d 02h /rtf65002/
24 - fixes to assembler robfinch 3977d 00h /rtf65002/
23 - added subtract immediate from sp
- added stack relative addressing mode
- added move positive, move negative instructions
- fix: TSA instruction		 robfinch 3977d 00h /rtf65002/
22 - fix indirect load robfinch 3978d 14h /rtf65002/
21 - config processor mode on reset
- D flag flags extended precision for add/sub
- added software interrupt call facility
- unimplmented opcode vectoring
- bus error signal support
- merge load states to reduce core size
- zero out ir during interrupt		 robfinch 3978d 19h /rtf65002/
20 - greater separation of emulation and native mode in source code
- fix instruction buffer fetch for non-cached accesses
- fix the sta (d),y instruction		 robfinch 3980d 01h /rtf65002/
19 - added multibit shifts
- added eight bit CMP instruction		 robfinch 3980d 23h /rtf65002/
18 - added shift instruction to assembler
- fixed acouple of minor bugs		 robfinch 3980d 23h /rtf65002/
17 - updated docs robfinch 3980d 23h /rtf65002/
16 - tiny basic robfinch 3981d 23h /rtf65002/
15 - updates to assembler
- interrupt support in bootrom.asm
-		 robfinch 3981d 23h /rtf65002/
14 - updated docs robfinch 3981d 23h /rtf65002/
13 - fix overflow in immediate mode
- fix bit instruction N,V setting
- add vector base register, modified interrupt vectoring		 robfinch 3982d 00h /rtf65002/
12 - added LFSR and TICK count special registers
- added MUL/DIV/MOD instructions		 robfinch 3983d 00h /rtf65002/
11 - added bootrom.asm
- fixed bugs in assembler		 robfinch 3985d 05h /rtf65002/
10 - fix rind mode in 32 bit mode
- fix flag update in 32 bit mode for RR instructions
- initialize cache tags
- added flag to disable ints until after sp load		 robfinch 3985d 05h /rtf65002/
9 updateing docs robfinch 3986d 05h /rtf65002/
8 updateing docs robfinch 3986d 05h /rtf65002/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.