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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] - Rev 41

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Rev Log message Author Age Path
41 - update for 65c816 support robfinch 3682d 02h /rtf65002/trunk/
40 - sample files in assembler robfinch 3682d 02h /rtf65002/trunk/
39 - updated assembler plus sample files robfinch 3682d 02h /rtf65002/trunk/
38 - updated to support the 65c816 opcodes robfinch 3682d 02h /rtf65002/trunk/
37 - latest documentation robfinch 3830d 21h /rtf65002/trunk/
36 - missing TRB/TSB instructions in 32 bit mode added robfinch 3830d 21h /rtf65002/trunk/
35 - several bug fixes
- mul,mod,div immediates mode than 8 bits
- page two opcode fix on cache miss
- setting upper pc bits in emulation mode (store)		 robfinch 3877d 14h /rtf65002/trunk/
34 - latest bootrom.asm
- and assembler		 robfinch 3888d 04h /rtf65002/trunk/
33 - most recent docs robfinch 3888d 04h /rtf65002/trunk/
32 - many changes
- new instructions
- code reorganization		 robfinch 3888d 04h /rtf65002/trunk/
31 - miscellaneous updates
- unimplemented instruction vector
-		 robfinch 3898d 01h /rtf65002/trunk/
30 - added additional branches
- modified the pc increment
- modified interrupts, all vector through BRK
- registered some decodes
- added SUPPORT macros to allow core trimming		 robfinch 3898d 02h /rtf65002/trunk/
29 - updated assembler, increased instruction support robfinch 3903d 21h /rtf65002/trunk/
28 - updated bootrom, robfinch 3903d 21h /rtf65002/trunk/
27 - most recent doc robfinch 3905d 03h /rtf65002/trunk/
26 - latest bootrom.asm
- fixes to assembler		 robfinch 3905d 03h /rtf65002/trunk/
25 - add EXEC and ATNI instructions
- fix store byte zero page indexed
- fix break instruction		 robfinch 3905d 03h /rtf65002/trunk/
24 - fixes to assembler robfinch 3911d 01h /rtf65002/trunk/
23 - added subtract immediate from sp
- added stack relative addressing mode
- added move positive, move negative instructions
- fix: TSA instruction		 robfinch 3911d 01h /rtf65002/trunk/
22 - fix indirect load robfinch 3912d 15h /rtf65002/trunk/
21 - config processor mode on reset
- D flag flags extended precision for add/sub
- added software interrupt call facility
- unimplmented opcode vectoring
- bus error signal support
- merge load states to reduce core size
- zero out ir during interrupt		 robfinch 3912d 20h /rtf65002/trunk/
20 - greater separation of emulation and native mode in source code
- fix instruction buffer fetch for non-cached accesses
- fix the sta (d),y instruction		 robfinch 3914d 03h /rtf65002/trunk/
19 - added multibit shifts
- added eight bit CMP instruction		 robfinch 3915d 01h /rtf65002/trunk/
18 - added shift instruction to assembler
- fixed acouple of minor bugs		 robfinch 3915d 01h /rtf65002/trunk/
17 - updated docs robfinch 3915d 01h /rtf65002/trunk/
16 - tiny basic robfinch 3916d 01h /rtf65002/trunk/
15 - updates to assembler
- interrupt support in bootrom.asm
-		 robfinch 3916d 01h /rtf65002/trunk/
14 - updated docs robfinch 3916d 01h /rtf65002/trunk/
13 - fix overflow in immediate mode
- fix bit instruction N,V setting
- add vector base register, modified interrupt vectoring		 robfinch 3916d 01h /rtf65002/trunk/
12 - added LFSR and TICK count special registers
- added MUL/DIV/MOD instructions		 robfinch 3917d 01h /rtf65002/trunk/

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