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[/] [s1_core/] [trunk/] [hdl/] - Rev 103

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Rev Log message Author Age Path
103 Changed almost everything to make our boot code work. fafa1971 5734d 01h /s1_core/trunk/hdl/
99 This bridge follows the rules stated in paragraph 6.8 of book "OpenSPARC Internals"
in order to stall all the threads while serving a single request.		 fafa1971 5739d 16h /s1_core/trunk/hdl/
98 Added stall/resume signals from bridge to SPARC Core. fafa1971 5739d 16h /s1_core/trunk/hdl/
96 File lists with updated SPARC Core code. fafa1971 5754d 22h /s1_core/trunk/hdl/
95 Files from OpenSPARCT1.1.6 with the SPU instance removed from the sparc.v top-level. fafa1971 5754d 22h /s1_core/trunk/hdl/
94 Removed files with dependencies from the SPU. fafa1971 5754d 22h /s1_core/trunk/hdl/
91 Filelists updated according to preprocessed files from OpenSPARC T1 1.6 fafa1971 5858d 15h /s1_core/trunk/hdl/
90 Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee" fafa1971 5858d 16h /s1_core/trunk/hdl/
89 Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me" fafa1971 5858d 16h /s1_core/trunk/hdl/
82 DC synthesis script modified according to the fabolous manual (RTFM...). fafa1971 6019d 23h /s1_core/trunk/hdl/
81 Sorry, I made a mistake in the waveform of the clock! fafa1971 6020d 02h /s1_core/trunk/hdl/
79 Relaxed timing, added flatten and hyerarchical report_area. fafa1971 6022d 22h /s1_core/trunk/hdl/
75 Changed preprocessing for DC synthesis fafa1971 6122d 23h /s1_core/trunk/hdl/
74 Updated filelists. fafa1971 6122d 23h /s1_core/trunk/hdl/
73 New version of scripts for DC and to compile boot code fafa1971 6123d 00h /s1_core/trunk/hdl/
58 These were only symbolic links to remember where such these things were defined fafa1971 6185d 15h /s1_core/trunk/hdl/
57 Latest version fafa1971 6185d 15h /s1_core/trunk/hdl/
56 Updated from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6185d 15h /s1_core/trunk/hdl/
55 Nobody remembers why these blackboxed files were required! fafa1971 6185d 15h /s1_core/trunk/hdl/
54 Updated filelists fafa1971 6185d 15h /s1_core/trunk/hdl/
53 Removed from CVS tree because header file preprocessing is done elsewhere fafa1971 6185d 15h /s1_core/trunk/hdl/
52 Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6185d 15h /s1_core/trunk/hdl/
51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6271d 15h /s1_core/trunk/hdl/
48 Updated with new OpenSPARC 1.4 list fafa1971 6336d 13h /s1_core/trunk/hdl/
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6336d 14h /s1_core/trunk/hdl/
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6336d 14h /s1_core/trunk/hdl/
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6337d 12h /s1_core/trunk/hdl/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6337d 12h /s1_core/trunk/hdl/
25 Updated filelists according to the new OpenSPARC 1.4, and add some minor
changes like Stephen Williams's suggestion to use $(S1_ROOT) in the filelists
for Icarus Verilog (he's the author!).		 fafa1971 6351d 15h /s1_core/trunk/hdl/
24 Fresh files taken from most recent OpenSPARC 1.4. fafa1971 6351d 15h /s1_core/trunk/hdl/

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