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[/] [s1_core/] [trunk/] [hdl/] [rtl/] - Rev 114

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Rev Log message Author Age Path
114 Change ownership albert.watson 2283d 14h /s1_core/trunk/hdl/rtl/
113 S1_Core: Attempt to merge some long time changes Fab had on his backups. albert.watson 2590d 11h /s1_core/trunk/hdl/rtl/
105 New directory structure. root 5570d 17h /s1_core/trunk/hdl/rtl/
103 Changed almost everything to make our boot code work. fafa1971 5667d 14h /s1_core/trunk/hdl/rtl/
99 This bridge follows the rules stated in paragraph 6.8 of book "OpenSPARC Internals"
in order to stall all the threads while serving a single request.		 fafa1971 5673d 04h /s1_core/trunk/hdl/rtl/
98 Added stall/resume signals from bridge to SPARC Core. fafa1971 5673d 05h /s1_core/trunk/hdl/rtl/
95 Files from OpenSPARCT1.1.6 with the SPU instance removed from the sparc.v top-level. fafa1971 5688d 10h /s1_core/trunk/hdl/rtl/
94 Removed files with dependencies from the SPU. fafa1971 5688d 10h /s1_core/trunk/hdl/rtl/
90 Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee" fafa1971 5792d 04h /s1_core/trunk/hdl/rtl/
89 Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me" fafa1971 5792d 04h /s1_core/trunk/hdl/rtl/
75 Changed preprocessing for DC synthesis fafa1971 6056d 11h /s1_core/trunk/hdl/rtl/
73 New version of scripts for DC and to compile boot code fafa1971 6056d 12h /s1_core/trunk/hdl/rtl/
58 These were only symbolic links to remember where such these things were defined fafa1971 6119d 03h /s1_core/trunk/hdl/rtl/
53 Removed from CVS tree because header file preprocessing is done elsewhere fafa1971 6119d 03h /s1_core/trunk/hdl/rtl/
52 Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6119d 03h /s1_core/trunk/hdl/rtl/
51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6205d 03h /s1_core/trunk/hdl/rtl/
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6270d 02h /s1_core/trunk/hdl/rtl/
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6270d 02h /s1_core/trunk/hdl/rtl/
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6271d 00h /s1_core/trunk/hdl/rtl/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6271d 00h /s1_core/trunk/hdl/rtl/
24 Fresh files taken from most recent OpenSPARC 1.4. fafa1971 6285d 03h /s1_core/trunk/hdl/rtl/
23 Fresh file taken from the most recent OpenSPARC 1.4. fafa1971 6285d 03h /s1_core/trunk/hdl/rtl/
22 Removed files of OpenSPARC 1.3 to later add the 1.4 ones. fafa1971 6285d 03h /s1_core/trunk/hdl/rtl/
21 Removed files of OpenSPARC 1.3 to later add version 1.4 ones. fafa1971 6285d 03h /s1_core/trunk/hdl/rtl/
20 Removed all the files of OpenSPARC 1.3 to later add the 1.4 ones. fafa1971 6285d 03h /s1_core/trunk/hdl/rtl/
19 *** empty log message *** fafa1971 6285d 04h /s1_core/trunk/hdl/rtl/
12 Updated the PCX/CPX fields description with all the info required for debugging. fafa1971 6345d 23h /s1_core/trunk/hdl/rtl/
11 Corrected the bug about the packet format, now we are near to perfection... fafa1971 6346d 02h /s1_core/trunk/hdl/rtl/
9 First release. fafa1971 6366d 23h /s1_core/trunk/hdl/rtl/
6 First version (from OpenSPARC 1.1.3). fafa1971 6367d 00h /s1_core/trunk/hdl/rtl/

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