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[/] [sdhc-sc-core/] - Rev 144

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144 Simulation files for tbTbdSd created.

tbTbdSd is not done and TestWbMaster seems to be lost.		 rkastl 4999d 02h /sdhc-sc-core/
143 Ignore pattern:
+ work
+ modelsim.ini
+ vsim.wlf
+ transcript
+ cycloneii and altera_mf generated library folders		 rkastl 4999d 02h /sdhc-sc-core/
142 Thesis: PDF added to .gitignore rkastl 4999d 02h /sdhc-sc-core/
141 Added *.bak to ignore file. rkastl 4999d 02h /sdhc-sc-core/
140 Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete
verification tb anyway.		 rkastl 4999d 02h /sdhc-sc-core/
139 Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in
the complete verification environment anyway.		 rkastl 4999d 02h /sdhc-sc-core/
138 Removed testbench for unitSdCmd because it was a weak testbench and the
functionality is tested in the SdVerificationTestbench anyway.		 rkastl 4999d 02h /sdhc-sc-core/
137 Regression test suite:

Removed unneeded testbenches from the makefile. Only complete reusable
blocks are tested from now on.		 rkastl 4999d 02h /sdhc-sc-core/
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4999d 02h /sdhc-sc-core/
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4999d 02h /sdhc-sc-core/
134 SdData: Further refactoring. rkastl 4999d 02h /sdhc-sc-core/
133 SdData: Further refactoring rkastl 4999d 02h /sdhc-sc-core/
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.		 rkastl 4999d 02h /sdhc-sc-core/
131 SdClockMaster added to regression tests rkastl 4999d 02h /sdhc-sc-core/
130 SdClockMaster: Formal verification rkastl 4999d 02h /sdhc-sc-core/
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4999d 02h /sdhc-sc-core/
128 Sim: Support for psl files added. rkastl 4999d 02h /sdhc-sc-core/
127 Thesis: Restructured SDHC chapter. rkastl 4999d 02h /sdhc-sc-core/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4999d 02h /sdhc-sc-core/
125 Write works in simulation rkastl 4999d 02h /sdhc-sc-core/
124 Write: SdClk is disabled, if no data is available. rkastl 4999d 02h /sdhc-sc-core/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4999d 02h /sdhc-sc-core/
122 SdController: Initial read support rkastl 4999d 05h /sdhc-sc-core/
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4999d 05h /sdhc-sc-core/
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4999d 05h /sdhc-sc-core/
119 SdWb: Synchronization of operation to SdController done, but needs
testing.		 rkastl 4999d 05h /sdhc-sc-core/
118 EdgeDetector added. rkastl 4999d 05h /sdhc-sc-core/
117 Removed unused units. rkastl 4999d 05h /sdhc-sc-core/
116 Wishbone interface for sd core started rkastl 4999d 05h /sdhc-sc-core/
115 WbSlave: New header. rkastl 4999d 05h /sdhc-sc-core/

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