OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 145

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
145 Verification:
+ SdCardModel and SdBFM seperated		 rkastl 4936d 07h /sdhc-sc-core/trunk/
144 Simulation files for tbTbdSd created.

tbTbdSd is not done and TestWbMaster seems to be lost.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
143 Ignore pattern:
+ work
+ modelsim.ini
+ vsim.wlf
+ transcript
+ cycloneii and altera_mf generated library folders		 rkastl 4936d 07h /sdhc-sc-core/trunk/
142 Thesis: PDF added to .gitignore rkastl 4936d 07h /sdhc-sc-core/trunk/
141 Added *.bak to ignore file. rkastl 4936d 07h /sdhc-sc-core/trunk/
140 Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete
verification tb anyway.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
139 Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in
the complete verification environment anyway.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
138 Removed testbench for unitSdCmd because it was a weak testbench and the
functionality is tested in the SdVerificationTestbench anyway.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
137 Regression test suite:

Removed unneeded testbenches from the makefile. Only complete reusable
blocks are tested from now on.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4936d 07h /sdhc-sc-core/trunk/
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
134 SdData: Further refactoring. rkastl 4936d 07h /sdhc-sc-core/trunk/
133 SdData: Further refactoring rkastl 4936d 07h /sdhc-sc-core/trunk/
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
131 SdClockMaster added to regression tests rkastl 4936d 07h /sdhc-sc-core/trunk/
130 SdClockMaster: Formal verification rkastl 4936d 07h /sdhc-sc-core/trunk/
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4936d 07h /sdhc-sc-core/trunk/
128 Sim: Support for psl files added. rkastl 4936d 07h /sdhc-sc-core/trunk/
127 Thesis: Restructured SDHC chapter. rkastl 4936d 07h /sdhc-sc-core/trunk/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4936d 07h /sdhc-sc-core/trunk/
125 Write works in simulation rkastl 4936d 07h /sdhc-sc-core/trunk/
124 Write: SdClk is disabled, if no data is available. rkastl 4936d 07h /sdhc-sc-core/trunk/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4936d 07h /sdhc-sc-core/trunk/
122 SdController: Initial read support rkastl 4936d 11h /sdhc-sc-core/trunk/
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4936d 11h /sdhc-sc-core/trunk/
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4936d 11h /sdhc-sc-core/trunk/
119 SdWb: Synchronization of operation to SdController done, but needs
testing.		 rkastl 4936d 11h /sdhc-sc-core/trunk/
118 EdgeDetector added. rkastl 4936d 11h /sdhc-sc-core/trunk/
117 Removed unused units. rkastl 4936d 11h /sdhc-sc-core/trunk/
116 Wishbone interface for sd core started rkastl 4936d 11h /sdhc-sc-core/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.