URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 166

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Rev	Log message	Author	Age	Path
166	tbTbdSd: fixed	rkastl	4928d 16h	/sdhc-sc-core/trunk/
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
164	Headers updated (LGPL, consistent format)	rkastl	4928d 16h	/sdhc-sc-core/trunk/
163	Header-Skript supports writing to file and infile replacement.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
162	Script for generating headers created.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
161	Verification: CardModel: Check CRC on received data	rkastl	4928d 16h	/sdhc-sc-core/trunk/
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
159	Verification: Further work: Checking RAM Actions and reading data is still missing	rkastl	4928d 16h	/sdhc-sc-core/trunk/
158	Verification: Work on Checking Functional coverage	rkastl	4928d 16h	/sdhc-sc-core/trunk/
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
156	SdVerification: + Split a SdCoreTransaction into multiple WbTransactions: Proof of Concept with a ReadSingleBlock-Transaction + Finish after certain amount of time and present simulation result	rkastl	4928d 16h	/sdhc-sc-core/trunk/
155	SdVerification: continue to work on it, not done.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
154	SdVerification: - started sending with mailboxes	rkastl	4928d 16h	/sdhc-sc-core/trunk/
153	SdVerification: further development, not done by far	rkastl	4928d 16h	/sdhc-sc-core/trunk/
152	SdClockMaster: Generate InStrobe so that it the sd bus gets captured on the rising edge of the clock in high speed mode	rkastl	4928d 16h	/sdhc-sc-core/trunk/
151	Verification: + redesign: not functional yet	rkastl	4928d 16h	/sdhc-sc-core/trunk/
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	4928d 16h	/sdhc-sc-core/trunk/
149	SdBFM: + mailbox mode	rkastl	4928d 16h	/sdhc-sc-core/trunk/
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4928d 16h	/sdhc-sc-core/trunk/
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4928d 16h	/sdhc-sc-core/trunk/
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4928d 16h	/sdhc-sc-core/trunk/
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
143	Ignore pattern: + work + modelsim.ini + vsim.wlf + transcript + cycloneii and altera_mf generated library folders	rkastl	4928d 16h	/sdhc-sc-core/trunk/
142	Thesis: PDF added to .gitignore	rkastl	4928d 16h	/sdhc-sc-core/trunk/
141	Added *.bak to ignore file.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4928d 16h	/sdhc-sc-core/trunk/
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4928d 16h	/sdhc-sc-core/trunk/

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[/] [sdhc-sc-core/] [trunk/] - Rev 166

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