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[/] [sdhc-sc-core/] [trunk/] - Rev 181

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181 Refs #60.

Fix synthesis with seperate WbClkDomain.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
180 Moved WbClkDomain to its own unit.
Refs #60.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
179 Fixing build:
Added library generation to Makefile.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4912d 20h /sdhc-sc-core/trunk/
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
175 Thesis:

Fixes #45.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
174 Thesis:
System integration

Fixes #51.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
173 Thesis:
Started with SdController description.

Refs #38.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
172 Thesis:
wbclockdomain: refactored and finished.

Fixes #39.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
170 License rewritten to BSD rkastl 4912d 20h /sdhc-sc-core/trunk/
169 +sdc file for timing analysis rkastl 4912d 20h /sdhc-sc-core/trunk/
168 TbdSd synthesis script reaches timing constraints. rkastl 4912d 20h /sdhc-sc-core/trunk/
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4912d 20h /sdhc-sc-core/trunk/
166 tbTbdSd: fixed rkastl 4912d 20h /sdhc-sc-core/trunk/
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4912d 20h /sdhc-sc-core/trunk/
164 Headers updated (LGPL, consistent format) rkastl 4912d 20h /sdhc-sc-core/trunk/
163 Header-Skript supports writing to file and infile replacement. rkastl 4912d 20h /sdhc-sc-core/trunk/
162 Script for generating headers created. rkastl 4912d 20h /sdhc-sc-core/trunk/
161 Verification:
CardModel: Check CRC on received data		 rkastl 4912d 20h /sdhc-sc-core/trunk/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4912d 20h /sdhc-sc-core/trunk/
158 Verification:
Work on Checking
Functional coverage		 rkastl 4912d 20h /sdhc-sc-core/trunk/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4912d 20h /sdhc-sc-core/trunk/
155 SdVerification:
continue to work on it, not done.		 rkastl 4912d 20h /sdhc-sc-core/trunk/
154 SdVerification:
- started sending with mailboxes		 rkastl 4912d 20h /sdhc-sc-core/trunk/
153 SdVerification:
further development, not done by far		 rkastl 4912d 20h /sdhc-sc-core/trunk/
152 SdClockMaster:
Generate InStrobe so that it the sd bus gets captured on the
rising edge of the clock in high speed mode		 rkastl 4912d 20h /sdhc-sc-core/trunk/

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