Rev |
Log message |
Author |
Age |
Path |
178 |
Fixed regression:
Testbenches did not support synchronous reset. |
rkastl |
4970d 23h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
176 |
Thesis:
Conclusion
Fixes #53,#61. |
rkastl |
4970d 23h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
170 |
License rewritten to BSD |
rkastl |
4970d 23h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
164 |
Headers updated (LGPL, consistent format) |
rkastl |
4970d 23h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
161 |
Verification:
CardModel: Check CRC on received data |
rkastl |
4970d 23h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
160 |
Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing. |
rkastl |
4970d 23h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
158 |
Verification:
Work on Checking
Functional coverage |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
157 |
Verification:
Testcase with Reads works but Verification not completly
implemented. |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
153 |
SdVerification:
further development, not done by far |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
147 |
Sd-Core:
+ Added checking of Busy signal after write |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
136 |
SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet) |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
126 |
Read and Write works in simulation, needs verification.
Synthesis works the same like before. |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
125 |
Write works in simulation |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
124 |
Write: SdClk is disabled, if no data is available. |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
123 |
Write: Must be able to halt SdClk, rest is done. |
rkastl |
4971d 00h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
122 |
SdController: Initial read support |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
113 |
Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc. |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
111 |
Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode). |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
109 |
Added a data ram. |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
108 |
Added a ram to the testbed |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
106 |
Fixes #29: All cards respond, but they do not all work. |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
105 |
Changing speed works! refs #33 |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
101 |
Receiving response to ACMD51 works including data, refs #33. |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
100 |
SdController: Receiving data after ACMD51, but CRC is wrong |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
94 |
CmdTimeout (8 Clocks) added, SdData inserted into top, refs #31 |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
89 |
Fixes #27, R3 uses '1111111' as CRC. |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
88 |
Timeouts inserted, Sending Card status via Rs232 if changed |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
85 |
Synthese: TbdSd refactored to enable sharing.
Sim: SdVerificationTestbench to new tcl script ported
SdController: TimeoutGenerator added, refs #27 |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
84 |
SdController: Refactored |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |
83 |
SdCmd: Refactored |
rkastl |
4971d 03h |
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/ |