URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 59

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Rev	Log message	Author	Age	Path
59	Control path request and data are register now for better FPGA timing	dinesha	4485d 09h	/sdr_ctrl/
58	Read Data is register on RD_FAST=0 case	dinesha	4485d 09h	/sdr_ctrl/
57	Synthesis constraints are added	dinesha	4486d 00h	/sdr_ctrl/
56	FPGA Synth optimisation	dinesha	4486d 01h	/sdr_ctrl/
55	FPGA Synthesis timing optimisation	dinesha	4486d 01h	/sdr_ctrl/
54	FPGA Timing Optimisation	dinesha	4488d 23h	/sdr_ctrl/
53	Test bench upgradation	dinesha	4489d 23h	/sdr_ctrl/
52	Documentation update for request control and transfer control block	dinesha	4489d 23h	/sdr_ctrl/
51	FPGA relating timing optimisation done	dinesha	4490d 00h	/sdr_ctrl/
50	Bug fix the request length is fixe	dinesha	4492d 03h	/sdr_ctrl/
49	clean up	dinesha	4493d 02h	/sdr_ctrl/
48	top-level cleanup	dinesha	4493d 02h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4493d 03h	/sdr_ctrl/
46	test bench upgrade + rtl cleanup	dinesha	4495d 03h	/sdr_ctrl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4495d 08h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4497d 06h	/sdr_ctrl/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4497d 07h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4497d 07h	/sdr_ctrl/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4497d 09h	/sdr_ctrl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4498d 02h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4498d 02h	/sdr_ctrl/
38	Port Name clean up	dinesha	4499d 07h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4499d 09h	/sdr_ctrl/
36	Clean up	dinesha	4500d 00h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4500d 01h	/sdr_ctrl/
34	Removed the older version	dinesha	4500d 01h	/sdr_ctrl/
33	clean up	dinesha	4500d 02h	/sdr_ctrl/
32	Debug is enable through +define	dinesha	4502d 01h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4502d 01h	/sdr_ctrl/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4502d 01h	/sdr_ctrl/

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Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 59

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