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[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 70

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4086d 11h /sdr_ctrl/trunk/rtl/
67 time scale removed dinesha 4156d 10h /sdr_ctrl/trunk/rtl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4404d 11h /sdr_ctrl/trunk/rtl/
64 CAS Latency support added for 4,5 dinesha 4404d 18h /sdr_ctrl/trunk/rtl/
61 RTL file list are added into SVN dinesha 4523d 18h /sdr_ctrl/trunk/rtl/
60 warning cleanup dinesha 4523d 18h /sdr_ctrl/trunk/rtl/
59 Control path request and data are register now for better FPGA timing dinesha 4523d 18h /sdr_ctrl/trunk/rtl/
58 Read Data is register on RD_FAST=0 case dinesha 4523d 18h /sdr_ctrl/trunk/rtl/
55 FPGA Synthesis timing optimisation dinesha 4524d 10h /sdr_ctrl/trunk/rtl/
54 FPGA Timing Optimisation dinesha 4527d 08h /sdr_ctrl/trunk/rtl/
51 FPGA relating timing optimisation done dinesha 4528d 09h /sdr_ctrl/trunk/rtl/
50 Bug fix the request length is fixe dinesha 4530d 12h /sdr_ctrl/trunk/rtl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4531d 12h /sdr_ctrl/trunk/rtl/
46 test bench upgrade + rtl cleanup dinesha 4533d 12h /sdr_ctrl/trunk/rtl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4533d 17h /sdr_ctrl/trunk/rtl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4535d 15h /sdr_ctrl/trunk/rtl/
42 Bug fix in read access is fixed dinesha 4535d 17h /sdr_ctrl/trunk/rtl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4536d 11h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4537d 16h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4537d 18h /sdr_ctrl/trunk/rtl/
36 Clean up dinesha 4538d 09h /sdr_ctrl/trunk/rtl/
33 clean up dinesha 4538d 11h /sdr_ctrl/trunk/rtl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4540d 10h /sdr_ctrl/trunk/rtl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4542d 14h /sdr_ctrl/trunk/rtl/
16 8 Bit SDRAM Support is added dinesha 4544d 09h /sdr_ctrl/trunk/rtl/
15 Port cleanup dinesha 4547d 10h /sdr_ctrl/trunk/rtl/
13 column bit are made progrmmable dinesha 4547d 10h /sdr_ctrl/trunk/rtl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4551d 11h /sdr_ctrl/trunk/rtl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4552d 08h /sdr_ctrl/trunk/rtl/
3 SDRAM controller core files are checked in dinesha 4558d 18h /sdr_ctrl/trunk/rtl/

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