URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 131

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Rev	Log message	Author	Age	Path
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3438d 11h	/socgen/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3542d 05h	/socgen/
129	removed unneeded 6502 files	jt_eaton	3997d 11h	/socgen/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3997d 11h	/socgen/
127	final cleanup before DAC	jt_eaton	4112d 07h	/socgen/
126	added mor1kx cleanup	jt_eaton	4165d 12h	/socgen/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4210d 06h	/socgen/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4263d 09h	/socgen/
123	added support for ubuntu 12.10	jt_eaton	4278d 01h	/socgen/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4286d 04h	/socgen/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4306d 10h	/socgen/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4324d 10h	/socgen/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4359d 05h	/socgen/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4394d 14h	/socgen/
117	added yellow pages tools	jt_eaton	4422d 09h	/socgen/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4457d 06h	/socgen/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4501d 10h	/socgen/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4513d 10h	/socgen/
113	started refactoring or1200	jt_eaton	4519d 02h	/socgen/
112	added more test sims removed unneeded files	jt_eaton	4528d 15h	/socgen/
111	split or1200 out into seperate test suite	jt_eaton	4530d 09h	/socgen/
110	split out more ip-xact components added sw sources	jt_eaton	4542d 07h	/socgen/
109	removed unused file	jt_eaton	4545d 07h	/socgen/
108	removed unneeded files	jt_eaton	4546d 13h	/socgen/
107	added designCfg files to all modules	jt_eaton	4546d 16h	/socgen/
106	checked in orp_soc project step 2	jt_eaton	4552d 09h	/socgen/
105	moved or1200_monitor from testbench to dut	jt_eaton	4555d 05h	/socgen/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4557d 06h	/socgen/
103	added user guide resynced to local repository	jt_eaton	4577d 06h	/socgen/
102	all ip-xact files now readable by kactus2	jt_eaton	4639d 02h	/socgen/

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[/] [socgen/] - Rev 131

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