URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 97

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Rev	Log message	Author	Age	Path
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4714d 10h	/socgen/
96	hierConnections now create ports	jt_eaton	4788d 06h	/socgen/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4797d 04h	/socgen/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4824d 06h	/socgen/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4836d 18h	/socgen/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4841d 19h	/socgen/
91	fixed all sims, coverage not working	jt_eaton	4849d 13h	/socgen/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4850d 06h	/socgen/
89	removed unneeded debug directories	jt_eaton	4871d 14h	/socgen/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4871d 14h	/socgen/
87	removed prebuilt geda schematics and symbols	jt_eaton	4882d 07h	/socgen/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4890d 04h	/socgen/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4897d 03h	/socgen/
84	removed unneeded files	jt_eaton	4947d 08h	/socgen/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4947d 12h	/socgen/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4962d 06h	/socgen/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4983d 13h	/socgen/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5013d 04h	/socgen/
79	removed unsupported code	jt_eaton	5019d 08h	/socgen/
78	removed unsupported fpga	jt_eaton	5019d 08h	/socgen/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	5019d 09h	/socgen/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5021d 14h	/socgen/
75	added linting using verilator	jt_eaton	5025d 06h	/socgen/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5030d 12h	/socgen/
73	removed dup png files	jt_eaton	5038d 11h	/socgen/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5038d 14h	/socgen/
71	ignore anything in work	jt_eaton	5045d 06h	/socgen/
70	ignore work	jt_eaton	5045d 06h	/socgen/
69	added work dir	jt_eaton	5045d 06h	/socgen/
68	moved to seperate components	jt_eaton	5048d 06h	/socgen/

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[/] [socgen/] - Rev 97

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