URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 102

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Rev	Log message	Author	Age	Path
102	all ip-xact files now readable by kactus2	jt_eaton	4611d 06h	/socgen/trunk/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4612d 08h	/socgen/trunk/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4624d 16h	/socgen/trunk/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4667d 08h	/socgen/trunk/
98	removed unneeded sim	jt_eaton	4703d 12h	/socgen/trunk/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4703d 13h	/socgen/trunk/
96	hierConnections now create ports	jt_eaton	4777d 09h	/socgen/trunk/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4786d 07h	/socgen/trunk/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4813d 08h	/socgen/trunk/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4825d 21h	/socgen/trunk/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4830d 22h	/socgen/trunk/
91	fixed all sims, coverage not working	jt_eaton	4838d 16h	/socgen/trunk/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4839d 08h	/socgen/trunk/
89	removed unneeded debug directories	jt_eaton	4860d 17h	/socgen/trunk/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4860d 17h	/socgen/trunk/
87	removed prebuilt geda schematics and symbols	jt_eaton	4871d 10h	/socgen/trunk/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4879d 07h	/socgen/trunk/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4886d 06h	/socgen/trunk/
84	removed unneeded files	jt_eaton	4936d 11h	/socgen/trunk/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4936d 15h	/socgen/trunk/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4951d 09h	/socgen/trunk/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4972d 16h	/socgen/trunk/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5002d 07h	/socgen/trunk/
79	removed unsupported code	jt_eaton	5008d 11h	/socgen/trunk/
78	removed unsupported fpga	jt_eaton	5008d 11h	/socgen/trunk/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	5008d 12h	/socgen/trunk/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5010d 17h	/socgen/trunk/
75	added linting using verilator	jt_eaton	5014d 09h	/socgen/trunk/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5019d 15h	/socgen/trunk/
73	removed dup png files	jt_eaton	5027d 14h	/socgen/trunk/

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[/] [socgen/] [trunk/] - Rev 102

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