URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 115

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Rev	Log message	Author	Age	Path
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4456d 04h	/socgen/trunk/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4468d 04h	/socgen/trunk/
113	started refactoring or1200	jt_eaton	4473d 20h	/socgen/trunk/
112	added more test sims removed unneeded files	jt_eaton	4483d 09h	/socgen/trunk/
111	split or1200 out into seperate test suite	jt_eaton	4485d 03h	/socgen/trunk/
110	split out more ip-xact components added sw sources	jt_eaton	4497d 01h	/socgen/trunk/
109	removed unused file	jt_eaton	4500d 01h	/socgen/trunk/
108	removed unneeded files	jt_eaton	4501d 07h	/socgen/trunk/
107	added designCfg files to all modules	jt_eaton	4501d 10h	/socgen/trunk/
106	checked in orp_soc project step 2	jt_eaton	4507d 03h	/socgen/trunk/
105	moved or1200_monitor from testbench to dut	jt_eaton	4509d 23h	/socgen/trunk/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4512d 00h	/socgen/trunk/
103	added user guide resynced to local repository	jt_eaton	4532d 00h	/socgen/trunk/
102	all ip-xact files now readable by kactus2	jt_eaton	4593d 20h	/socgen/trunk/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4594d 21h	/socgen/trunk/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4607d 05h	/socgen/trunk/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4649d 22h	/socgen/trunk/
98	removed unneeded sim	jt_eaton	4686d 01h	/socgen/trunk/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4686d 03h	/socgen/trunk/
96	hierConnections now create ports	jt_eaton	4759d 23h	/socgen/trunk/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4768d 21h	/socgen/trunk/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4795d 22h	/socgen/trunk/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4808d 10h	/socgen/trunk/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4813d 11h	/socgen/trunk/
91	fixed all sims, coverage not working	jt_eaton	4821d 06h	/socgen/trunk/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4821d 22h	/socgen/trunk/
89	removed unneeded debug directories	jt_eaton	4843d 06h	/socgen/trunk/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4843d 06h	/socgen/trunk/
87	removed prebuilt geda schematics and symbols	jt_eaton	4853d 23h	/socgen/trunk/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4861d 20h	/socgen/trunk/

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Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 115

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