OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5102d 15h /socgen/trunk/
73 removed dup png files jt_eaton 5110d 15h /socgen/trunk/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog		 jt_eaton 5110d 17h /socgen/trunk/
71 ignore anything in work jt_eaton 5117d 10h /socgen/trunk/
70 ignore work jt_eaton 5117d 10h /socgen/trunk/
69 added work dir jt_eaton 5117d 10h /socgen/trunk/
68 moved to seperate components jt_eaton 5120d 10h /socgen/trunk/
67 updated installs jt_eaton 5120d 10h /socgen/trunk/
66 converted sims to use parameters
added msp and 6502 software installs		 jt_eaton 5121d 09h /socgen/trunk/
65 added params.sim to sims
updated install's		 jt_eaton 5126d 10h /socgen/trunk/
64 added support for Fedora 13 jt_eaton 5130d 08h /socgen/trunk/
63 added install config for Ubuntu 10.10 jt_eaton 5130d 15h /socgen/trunk/
62 fixed parameters from `defines jt_eaton 5134d 07h /socgen/trunk/
61 now generate dut files for coverage
removed use of lndir		 jt_eaton 5134d 09h /socgen/trunk/
60 moved alu_logic into seperate component jt_eaton 5134d 20h /socgen/trunk/
59 added filelist.core to syn dirs to customize core jt_eaton 5134d 20h /socgen/trunk/
58 removed old Makefiles jt_eaton 5135d 11h /socgen/trunk/
57 Now generate all filelists from xml files jt_eaton 5135d 12h /socgen/trunk/
56 soc_builder now builds verilog from xml files jt_eaton 5140d 20h /socgen/trunk/
55 removed pre-rout and gates sims jt_eaton 5143d 16h /socgen/trunk/
54 now set up fpga targets from xml files jt_eaton 5143d 18h /socgen/trunk/
53 fixed check_fpgas jt_eaton 5146d 07h /socgen/trunk/
52 removed noworking sims and syn jt_eaton 5146d 08h /socgen/trunk/
51 removed old test jt_eaton 5146d 08h /socgen/trunk/
50 clean up from last checkin jt_eaton 5146d 08h /socgen/trunk/
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5146d 11h /socgen/trunk/
48 added support for covered code checking jt_eaton 5168d 17h /socgen/trunk/
47 removed old variant jt_eaton 5182d 20h /socgen/trunk/
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5182d 20h /socgen/trunk/
45 added 6502 sims/software and synth jt_eaton 5189d 16h /socgen/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.