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[/] [socgen/] [trunk/] - Rev 80

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Rev Log message Author Age Path
80 now generate all sims and syns param and filelists for xml jt_eaton 5019d 21h /socgen/trunk/
79 removed unsupported code jt_eaton 5026d 02h /socgen/trunk/
78 removed unsupported fpga jt_eaton 5026d 02h /socgen/trunk/
77 now generate syn and cov Makefiles
leave log and out files in sim/run directory		 jt_eaton 5026d 03h /socgen/trunk/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory		 jt_eaton 5028d 08h /socgen/trunk/
75 added linting using verilator jt_eaton 5032d 00h /socgen/trunk/
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5037d 05h /socgen/trunk/
73 removed dup png files jt_eaton 5045d 05h /socgen/trunk/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog		 jt_eaton 5045d 07h /socgen/trunk/
71 ignore anything in work jt_eaton 5052d 00h /socgen/trunk/
70 ignore work jt_eaton 5052d 00h /socgen/trunk/
69 added work dir jt_eaton 5052d 00h /socgen/trunk/
68 moved to seperate components jt_eaton 5055d 00h /socgen/trunk/
67 updated installs jt_eaton 5055d 00h /socgen/trunk/
66 converted sims to use parameters
added msp and 6502 software installs		 jt_eaton 5055d 23h /socgen/trunk/
65 added params.sim to sims
updated install's		 jt_eaton 5061d 00h /socgen/trunk/
64 added support for Fedora 13 jt_eaton 5064d 22h /socgen/trunk/
63 added install config for Ubuntu 10.10 jt_eaton 5065d 05h /socgen/trunk/
62 fixed parameters from `defines jt_eaton 5068d 21h /socgen/trunk/
61 now generate dut files for coverage
removed use of lndir		 jt_eaton 5068d 23h /socgen/trunk/
60 moved alu_logic into seperate component jt_eaton 5069d 10h /socgen/trunk/
59 added filelist.core to syn dirs to customize core jt_eaton 5069d 10h /socgen/trunk/
58 removed old Makefiles jt_eaton 5070d 01h /socgen/trunk/
57 Now generate all filelists from xml files jt_eaton 5070d 02h /socgen/trunk/
56 soc_builder now builds verilog from xml files jt_eaton 5075d 10h /socgen/trunk/
55 removed pre-rout and gates sims jt_eaton 5078d 06h /socgen/trunk/
54 now set up fpga targets from xml files jt_eaton 5078d 07h /socgen/trunk/
53 fixed check_fpgas jt_eaton 5080d 21h /socgen/trunk/
52 removed noworking sims and syn jt_eaton 5080d 21h /socgen/trunk/
51 removed old test jt_eaton 5080d 21h /socgen/trunk/

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