URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 133

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Rev	Log message	Author	Age	Path
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3362d 08h	/socgen/trunk/tools/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3394d 05h	/socgen/trunk/tools/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3497d 23h	/socgen/trunk/tools/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3953d 05h	/socgen/trunk/tools/
127	final cleanup before DAC	jt_eaton	4068d 01h	/socgen/trunk/tools/
126	added mor1kx cleanup	jt_eaton	4121d 06h	/socgen/trunk/tools/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4166d 00h	/socgen/trunk/tools/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4219d 03h	/socgen/trunk/tools/
123	added support for ubuntu 12.10	jt_eaton	4233d 19h	/socgen/trunk/tools/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4241d 22h	/socgen/trunk/tools/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4262d 04h	/socgen/trunk/tools/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4280d 04h	/socgen/trunk/tools/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4314d 23h	/socgen/trunk/tools/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4350d 08h	/socgen/trunk/tools/
117	added yellow pages tools	jt_eaton	4378d 03h	/socgen/trunk/tools/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4413d 00h	/socgen/trunk/tools/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4457d 04h	/socgen/trunk/tools/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4469d 04h	/socgen/trunk/tools/
113	started refactoring or1200	jt_eaton	4474d 20h	/socgen/trunk/tools/
112	added more test sims removed unneeded files	jt_eaton	4484d 09h	/socgen/trunk/tools/
110	split out more ip-xact components added sw sources	jt_eaton	4498d 01h	/socgen/trunk/tools/
107	added designCfg files to all modules	jt_eaton	4502d 10h	/socgen/trunk/tools/
106	checked in orp_soc project step 2	jt_eaton	4508d 03h	/socgen/trunk/tools/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4513d 00h	/socgen/trunk/tools/
103	added user guide resynced to local repository	jt_eaton	4533d 00h	/socgen/trunk/tools/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4595d 21h	/socgen/trunk/tools/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4608d 05h	/socgen/trunk/tools/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4650d 21h	/socgen/trunk/tools/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4687d 03h	/socgen/trunk/tools/
96	hierConnections now create ports	jt_eaton	4760d 23h	/socgen/trunk/tools/

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[/] [socgen/] [trunk/] [tools/] - Rev 133

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