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[/] [socgen/] [trunk/] [tools/] - Rev 94

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Rev Log message Author Age Path
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4801d 05h /socgen/trunk/tools/
93 build scripts now support model views
linting and coverage starting to work again		 jt_eaton 4813d 18h /socgen/trunk/tools/
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench		 jt_eaton 4818d 19h /socgen/trunk/tools/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4827d 05h /socgen/trunk/tools/
88 added xml files for test benches
added gEDA sym sch starter templates		 jt_eaton 4848d 14h /socgen/trunk/tools/
86 split out all fpgas into families
added fpga pad_ring level		 jt_eaton 4867d 04h /socgen/trunk/tools/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines		 jt_eaton 4874d 03h /socgen/trunk/tools/
84 removed unneeded files jt_eaton 4924d 08h /socgen/trunk/tools/
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4924d 12h /socgen/trunk/tools/
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 4939d 06h /socgen/trunk/tools/
81 morphing xml files to use 1685
removed log directories		 jt_eaton 4960d 13h /socgen/trunk/tools/
80 now generate all sims and syns param and filelists for xml jt_eaton 4990d 04h /socgen/trunk/tools/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory		 jt_eaton 4998d 14h /socgen/trunk/tools/
75 added linting using verilator jt_eaton 5002d 06h /socgen/trunk/tools/
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5007d 11h /socgen/trunk/tools/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog		 jt_eaton 5015d 13h /socgen/trunk/tools/
67 updated installs jt_eaton 5025d 06h /socgen/trunk/tools/
66 converted sims to use parameters
added msp and 6502 software installs		 jt_eaton 5026d 05h /socgen/trunk/tools/
65 added params.sim to sims
updated install's		 jt_eaton 5031d 06h /socgen/trunk/tools/
64 added support for Fedora 13 jt_eaton 5035d 05h /socgen/trunk/tools/
63 added install config for Ubuntu 10.10 jt_eaton 5035d 11h /socgen/trunk/tools/
61 now generate dut files for coverage
removed use of lndir		 jt_eaton 5039d 05h /socgen/trunk/tools/
59 added filelist.core to syn dirs to customize core jt_eaton 5039d 16h /socgen/trunk/tools/
57 Now generate all filelists from xml files jt_eaton 5040d 08h /socgen/trunk/tools/
56 soc_builder now builds verilog from xml files jt_eaton 5045d 16h /socgen/trunk/tools/
54 now set up fpga targets from xml files jt_eaton 5048d 14h /socgen/trunk/tools/
50 clean up from last checkin jt_eaton 5051d 04h /socgen/trunk/tools/
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5051d 07h /socgen/trunk/tools/
48 added support for covered code checking jt_eaton 5073d 13h /socgen/trunk/tools/
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5087d 16h /socgen/trunk/tools/

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