URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 124

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Rev	Log message	Author	Age	Path
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4219d 03h	/socgen/trunk/tools/bin/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4280d 05h	/socgen/trunk/tools/bin/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4314d 23h	/socgen/trunk/tools/bin/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4350d 08h	/socgen/trunk/tools/bin/
117	added yellow pages tools	jt_eaton	4378d 03h	/socgen/trunk/tools/bin/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4469d 04h	/socgen/trunk/tools/bin/
113	started refactoring or1200	jt_eaton	4474d 21h	/socgen/trunk/tools/bin/
112	added more test sims removed unneeded files	jt_eaton	4484d 09h	/socgen/trunk/tools/bin/
106	checked in orp_soc project step 2	jt_eaton	4508d 03h	/socgen/trunk/tools/bin/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4608d 05h	/socgen/trunk/tools/bin/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4650d 22h	/socgen/trunk/tools/bin/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4687d 03h	/socgen/trunk/tools/bin/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4796d 22h	/socgen/trunk/tools/bin/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4809d 11h	/socgen/trunk/tools/bin/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4822d 22h	/socgen/trunk/tools/bin/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4844d 07h	/socgen/trunk/tools/bin/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4862d 21h	/socgen/trunk/tools/bin/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4869d 19h	/socgen/trunk/tools/bin/
84	removed unneeded files	jt_eaton	4920d 01h	/socgen/trunk/tools/bin/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4920d 05h	/socgen/trunk/tools/bin/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4934d 23h	/socgen/trunk/tools/bin/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4956d 05h	/socgen/trunk/tools/bin/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4985d 20h	/socgen/trunk/tools/bin/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	4994d 07h	/socgen/trunk/tools/bin/
75	added linting using verilator	jt_eaton	4997d 23h	/socgen/trunk/tools/bin/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5003d 04h	/socgen/trunk/tools/bin/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5011d 06h	/socgen/trunk/tools/bin/
67	updated installs	jt_eaton	5020d 23h	/socgen/trunk/tools/bin/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5021d 22h	/socgen/trunk/tools/bin/
65	added params.sim to sims updated install's	jt_eaton	5026d 23h	/socgen/trunk/tools/bin/

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 124

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