URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 134

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Rev	Log message	Author	Age	Path
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3354d 21h	/socgen/trunk/tools/bin/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3429d 19h	/socgen/trunk/tools/bin/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3533d 12h	/socgen/trunk/tools/bin/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3988d 18h	/socgen/trunk/tools/bin/
126	added mor1kx cleanup	jt_eaton	4156d 20h	/socgen/trunk/tools/bin/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4201d 13h	/socgen/trunk/tools/bin/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4254d 16h	/socgen/trunk/tools/bin/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4315d 18h	/socgen/trunk/tools/bin/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4350d 12h	/socgen/trunk/tools/bin/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4385d 22h	/socgen/trunk/tools/bin/
117	added yellow pages tools	jt_eaton	4413d 16h	/socgen/trunk/tools/bin/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4504d 18h	/socgen/trunk/tools/bin/
113	started refactoring or1200	jt_eaton	4510d 10h	/socgen/trunk/tools/bin/
112	added more test sims removed unneeded files	jt_eaton	4519d 23h	/socgen/trunk/tools/bin/
106	checked in orp_soc project step 2	jt_eaton	4543d 17h	/socgen/trunk/tools/bin/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4643d 19h	/socgen/trunk/tools/bin/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4686d 11h	/socgen/trunk/tools/bin/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4722d 17h	/socgen/trunk/tools/bin/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4832d 12h	/socgen/trunk/tools/bin/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4845d 00h	/socgen/trunk/tools/bin/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4858d 12h	/socgen/trunk/tools/bin/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4879d 20h	/socgen/trunk/tools/bin/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4898d 10h	/socgen/trunk/tools/bin/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4905d 09h	/socgen/trunk/tools/bin/
84	removed unneeded files	jt_eaton	4955d 14h	/socgen/trunk/tools/bin/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4955d 18h	/socgen/trunk/tools/bin/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4970d 13h	/socgen/trunk/tools/bin/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4991d 19h	/socgen/trunk/tools/bin/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5021d 10h	/socgen/trunk/tools/bin/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5029d 20h	/socgen/trunk/tools/bin/

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 134

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