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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 94

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Rev Log message Author Age Path
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4789d 17h /socgen/trunk/tools/bin/
93 build scripts now support model views
linting and coverage starting to work again		 jt_eaton 4802d 05h /socgen/trunk/tools/bin/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4815d 17h /socgen/trunk/tools/bin/
88 added xml files for test benches
added gEDA sym sch starter templates		 jt_eaton 4837d 01h /socgen/trunk/tools/bin/
86 split out all fpgas into families
added fpga pad_ring level		 jt_eaton 4855d 15h /socgen/trunk/tools/bin/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines		 jt_eaton 4862d 14h /socgen/trunk/tools/bin/
84 removed unneeded files jt_eaton 4912d 19h /socgen/trunk/tools/bin/
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4913d 00h /socgen/trunk/tools/bin/
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 4927d 18h /socgen/trunk/tools/bin/
81 morphing xml files to use 1685
removed log directories		 jt_eaton 4949d 00h /socgen/trunk/tools/bin/
80 now generate all sims and syns param and filelists for xml jt_eaton 4978d 15h /socgen/trunk/tools/bin/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory		 jt_eaton 4987d 01h /socgen/trunk/tools/bin/
75 added linting using verilator jt_eaton 4990d 18h /socgen/trunk/tools/bin/
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 4995d 23h /socgen/trunk/tools/bin/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog		 jt_eaton 5004d 01h /socgen/trunk/tools/bin/
67 updated installs jt_eaton 5013d 17h /socgen/trunk/tools/bin/
66 converted sims to use parameters
added msp and 6502 software installs		 jt_eaton 5014d 17h /socgen/trunk/tools/bin/
65 added params.sim to sims
updated install's		 jt_eaton 5019d 17h /socgen/trunk/tools/bin/
61 now generate dut files for coverage
removed use of lndir		 jt_eaton 5027d 16h /socgen/trunk/tools/bin/
59 added filelist.core to syn dirs to customize core jt_eaton 5028d 04h /socgen/trunk/tools/bin/
57 Now generate all filelists from xml files jt_eaton 5028d 19h /socgen/trunk/tools/bin/
56 soc_builder now builds verilog from xml files jt_eaton 5034d 04h /socgen/trunk/tools/bin/
54 now set up fpga targets from xml files jt_eaton 5037d 01h /socgen/trunk/tools/bin/
50 clean up from last checkin jt_eaton 5039d 16h /socgen/trunk/tools/bin/
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5039d 19h /socgen/trunk/tools/bin/
48 added support for covered code checking jt_eaton 5062d 01h /socgen/trunk/tools/bin/
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5076d 04h /socgen/trunk/tools/bin/
41 added kim-1 design and program
now support Nexys2 sdram		 jt_eaton 5111d 02h /socgen/trunk/tools/bin/
20 added Nexys2 support
expanded docs
created tools directory		 jt_eaton 5174d 15h /socgen/trunk/tools/bin/

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