URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 134

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Rev	Log message	Author	Age	Path
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3354d 21h	/socgen/trunk/tools/sys/
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3397d 22h	/socgen/trunk/tools/sys/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3429d 19h	/socgen/trunk/tools/sys/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3533d 12h	/socgen/trunk/tools/sys/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3988d 18h	/socgen/trunk/tools/sys/
127	final cleanup before DAC	jt_eaton	4103d 15h	/socgen/trunk/tools/sys/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4201d 13h	/socgen/trunk/tools/sys/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4254d 16h	/socgen/trunk/tools/sys/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4297d 18h	/socgen/trunk/tools/sys/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4315d 18h	/socgen/trunk/tools/sys/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4350d 12h	/socgen/trunk/tools/sys/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4385d 21h	/socgen/trunk/tools/sys/
117	added yellow pages tools	jt_eaton	4413d 16h	/socgen/trunk/tools/sys/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4448d 13h	/socgen/trunk/tools/sys/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4492d 18h	/socgen/trunk/tools/sys/
110	split out more ip-xact components added sw sources	jt_eaton	4533d 15h	/socgen/trunk/tools/sys/
107	added designCfg files to all modules	jt_eaton	4537d 23h	/socgen/trunk/tools/sys/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4548d 13h	/socgen/trunk/tools/sys/
103	added user guide resynced to local repository	jt_eaton	4568d 14h	/socgen/trunk/tools/sys/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4631d 11h	/socgen/trunk/tools/sys/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4643d 19h	/socgen/trunk/tools/sys/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4686d 11h	/socgen/trunk/tools/sys/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4722d 16h	/socgen/trunk/tools/sys/
96	hierConnections now create ports	jt_eaton	4796d 13h	/socgen/trunk/tools/sys/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4805d 10h	/socgen/trunk/tools/sys/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4832d 12h	/socgen/trunk/tools/sys/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4845d 00h	/socgen/trunk/tools/sys/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4850d 01h	/socgen/trunk/tools/sys/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4858d 12h	/socgen/trunk/tools/sys/

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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 134

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