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[/] [storm_core/] - Rev 37

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Rev Log message Author Age Path
37 remove project zero_gravity 781d 06h /storm_core/
36 - sources of storm_extractor added zero_gravity 4026d 10h /storm_core/
35 - fixed bug in SP write back of LDM operations
- fixed bug in opcode decoding of SWI instruction
- documentary update
zero_gravity 4405d 11h /storm_core/
34 - bug fixed in carry-flag generation logic (not-carry = borrow flag)
- missing signal in STORM_TOP.vhd added
zero_gravity 4445d 22h /storm_core/
33 - branch-and-exchange instruction (BX) support added
=> for BX Rn, where Rn(0) = '0', behavior like branch to address = Rn
=> for BX Rn, where Rn(0) = '1', triggering undefined instruction trap
zero_gravity 4452d 07h /storm_core/
32 - bug-fix of block transfer operations
=> now fully ARM-compatible
zero_gravity 4453d 19h /storm_core/
31 - small documentary edits
- CACHE.vhd modified for better synthesis results
- BUS_UNIT.vhd update to fulfill WB specs
zero_gravity 4456d 05h /storm_core/
30 - minor edits in doc zero_gravity 4461d 05h /storm_core/
29 - specific IO area is now auto protected
- Wishbone compatibility extended
- cache flush optimized
- accelerated bus cycles due to less overhead
zero_gravity 4462d 06h /storm_core/
28 - bugfix in pipeline re-sync of d/i-cache
- optimized bus unit
- minor edits... ^^
zero_gravity 4473d 08h /storm_core/
27 updated "sim" folder
- error in testbench environment
-> old components
-> weren't compatible to new core version anymore
=> FIXED! ;)
- thanks to Pratip Mukherjee
zero_gravity 4477d 08h /storm_core/
26 bug fixes:
- change in priority for cache miss/dirty/io_access
- memory based pc modifications
- removed internal timer
zero_gravity 4478d 08h /storm_core/
25 bug-fix in cache component:
-> error in cache page-access history manager
zero_gravity 4486d 16h /storm_core/
24 - changed back to original oc svn folder structure
- bug-fix in documentary
- WB_ERR_I signal added to terminate wishbone bus access
- bug-fix: system mode register set and privs
zero_gravity 4487d 15h /storm_core/
23 zero_gravity 4487d 15h /storm_core/
22 changed back to original svn folder structure zero_gravity 4487d 15h /storm_core/
21 smaller, faster, better ;)
* bug-fix: load-multiple instructions
* new cache-control system
* direct-accessible IO area can be specified
* extended demo implementation
zero_gravity 4494d 10h /storm_core/
20 - update of data sheet -> note for system memory map layout and d-cache configuration zero_gravity 4510d 05h /storm_core/
19 - simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated
zero_gravity 4510d 09h /storm_core/
18 makefile update to ensure no thumb code is generated zero_gravity 4515d 13h /storm_core/
17 small synthesis-friendly update of memory components zero_gravity 4518d 07h /storm_core/
16 WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed
zero_gravity 4518d 09h /storm_core/
15 new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) zero_gravity 4518d 13h /storm_core/
14 - corrected stupid error in access arbiter
- updated minor issues
zero_gravity 4656d 09h /storm_core/
13 - corrected endianess converter for memory access
- corrected error in temporal dependence detector
zero_gravity 4657d 05h /storm_core/
12 - corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access
zero_gravity 4657d 11h /storm_core/
11 zero_gravity 4660d 15h /storm_core/
10 New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included.
zero_gravity 4660d 15h /storm_core/
9 documentation updated zero_gravity 4750d 13h /storm_core/
8 documentation uploaded ;) zero_gravity 4752d 07h /storm_core/

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