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[/] [t48/] [tags/] [rel_0_1_beta/] [rtl/] [vhdl/] - Rev 304

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Rev Log message Author Age Path
292 New directory structure. root 5610d 02h /t48/tags/rel_0_1_beta/rtl/vhdl/
251 This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'. 6580d 10h /t48/tags/rel_0_1_beta/rtl/vhdl/
86 update notice about expander port instructions arniml 7384d 00h /t48/tags/rel_0_1_beta/rtl/vhdl/
78 adjust external timing of BUS arniml 7389d 19h /t48/tags/rel_0_1_beta/rtl/vhdl/
77 move from std_logic_arith to numeric_std arniml 7390d 12h /t48/tags/rel_0_1_beta/rtl/vhdl/
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7391d 00h /t48/tags/rel_0_1_beta/rtl/vhdl/
72 removed superfluous signal from sensitivity list arniml 7391d 00h /t48/tags/rel_0_1_beta/rtl/vhdl/
66 add temporary workaround for GHDL 0.11 arniml 7396d 17h /t48/tags/rel_0_1_beta/rtl/vhdl/
65 clean up sensitivity list arniml 7396d 17h /t48/tags/rel_0_1_beta/rtl/vhdl/
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions		 arniml 7396d 17h /t48/tags/rel_0_1_beta/rtl/vhdl/
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset		 arniml 7396d 17h /t48/tags/rel_0_1_beta/rtl/vhdl/
62 initial check-in arniml 7396d 17h /t48/tags/rel_0_1_beta/rtl/vhdl/
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls		 arniml 7399d 13h /t48/tags/rel_0_1_beta/rtl/vhdl/
59 increment prescaler with MSTATE4 arniml 7399d 13h /t48/tags/rel_0_1_beta/rtl/vhdl/
54 - add tb_istrobe_s arniml 7400d 15h /t48/tags/rel_0_1_beta/rtl/vhdl/
53 make istrobe visible through testbench package arniml 7400d 15h /t48/tags/rel_0_1_beta/rtl/vhdl/
45 remove unused signals arniml 7407d 13h /t48/tags/rel_0_1_beta/rtl/vhdl/
44 default assignment for aux_carry_o arniml 7407d 15h /t48/tags/rel_0_1_beta/rtl/vhdl/
43 fix sensitivity list arniml 7408d 15h /t48/tags/rel_0_1_beta/rtl/vhdl/
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7408d 17h /t48/tags/rel_0_1_beta/rtl/vhdl/
38 add measures to implement XCHD arniml 7410d 21h /t48/tags/rel_0_1_beta/rtl/vhdl/
37 add dump_compare support arniml 7410d 21h /t48/tags/rel_0_1_beta/rtl/vhdl/
32 rename pX_limp to pX_low_imp arniml 7416d 16h /t48/tags/rel_0_1_beta/rtl/vhdl/
29 take auxiliary carry from direct ALU connection arniml 7417d 14h /t48/tags/rel_0_1_beta/rtl/vhdl/
28 update wiring for DA support arniml 7417d 14h /t48/tags/rel_0_1_beta/rtl/vhdl/
27 implemented mnemonic DA arniml 7417d 14h /t48/tags/rel_0_1_beta/rtl/vhdl/
26 support for DA instruction arniml 7417d 14h /t48/tags/rel_0_1_beta/rtl/vhdl/
24 connect control signal for Port 2 expander arniml 7417d 22h /t48/tags/rel_0_1_beta/rtl/vhdl/
23 rework Port 2 expander handling arniml 7417d 22h /t48/tags/rel_0_1_beta/rtl/vhdl/
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7417d 22h /t48/tags/rel_0_1_beta/rtl/vhdl/

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