OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] - Rev 333

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5598d 20h /t48/tags/rel_0_2_beta/sw/
252 This commit was manufactured by cvs2svn to create tag 'rel_0_2_beta'. 6569d 04h /t48/tags/rel_0_2_beta/sw/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7352d 18h /t48/tags/rel_0_2_beta/sw/
104 add white_box directory to test suite arniml 7356d 15h /t48/tags/rel_0_2_beta/sw/
102 update for changes in address space of external memory arniml 7356d 15h /t48/tags/rel_0_2_beta/sw/
99 initial check-in arniml 7356d 15h /t48/tags/rel_0_2_beta/sw/
97 initial check-in arniml 7356d 16h /t48/tags/rel_0_2_beta/sw/
96 select dedicated directorie(s) for regression arniml 7357d 13h /t48/tags/rel_0_2_beta/sw/
95 check counter inactivity arniml 7357d 13h /t48/tags/rel_0_2_beta/sw/
94 initial check-in arniml 7357d 13h /t48/tags/rel_0_2_beta/sw/
90 intial check-in arniml 7357d 14h /t48/tags/rel_0_2_beta/sw/
89 initial check-in arniml 7371d 10h /t48/tags/rel_0_2_beta/sw/
88 allow memory bank switching during interrupts arniml 7372d 12h /t48/tags/rel_0_2_beta/sw/
87 abort gracfullt if memory bank switching does not work arniml 7372d 12h /t48/tags/rel_0_2_beta/sw/
85 initial check-in arniml 7372d 18h /t48/tags/rel_0_2_beta/sw/
74 enhance pass/fail detection arniml 7379d 18h /t48/tags/rel_0_2_beta/sw/
70 clean test cell before make arniml 7385d 11h /t48/tags/rel_0_2_beta/sw/
69 fix name of istrobe arniml 7385d 11h /t48/tags/rel_0_2_beta/sw/
61 expand script for dump compare arniml 7387d 07h /t48/tags/rel_0_2_beta/sw/
58 add periodic interrupt arniml 7388d 07h /t48/tags/rel_0_2_beta/sw/
57 abort if no interrupt occurs arniml 7388d 08h /t48/tags/rel_0_2_beta/sw/
52 + fix bug in PSW[3]
+ read SP properly for dump
arniml 7389d 09h /t48/tags/rel_0_2_beta/sw/
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents
arniml 7389d 09h /t48/tags/rel_0_2_beta/sw/
49 Imported sources arniml 7394d 10h /t48/tags/rel_0_2_beta/sw/
48 update copyright notice arniml 7394d 10h /t48/tags/rel_0_2_beta/sw/
47 initial check-in arniml 7394d 10h /t48/tags/rel_0_2_beta/sw/
46 fix test arniml 7396d 07h /t48/tags/rel_0_2_beta/sw/
42 change test values that match better to the test case arniml 7397d 11h /t48/tags/rel_0_2_beta/sw/
41 expand PATH arniml 7397d 11h /t48/tags/rel_0_2_beta/sw/
39 initial check-in arniml 7399d 15h /t48/tags/rel_0_2_beta/sw/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.