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[/] [t48/] [tags/] [rel_0_3_beta/] - Rev 47

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Rev Log message Author Age Path
47 initial check-in arniml 7403d 03h /t48/tags/rel_0_3_beta/
46 fix test arniml 7405d 00h /t48/tags/rel_0_3_beta/
45 remove unused signals arniml 7405d 00h /t48/tags/rel_0_3_beta/
44 default assignment for aux_carry_o arniml 7405d 01h /t48/tags/rel_0_3_beta/
43 fix sensitivity list arniml 7406d 02h /t48/tags/rel_0_3_beta/
42 change test values that match better to the test case arniml 7406d 04h /t48/tags/rel_0_3_beta/
41 expand PATH arniml 7406d 04h /t48/tags/rel_0_3_beta/
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7406d 04h /t48/tags/rel_0_3_beta/
39 initial check-in arniml 7408d 08h /t48/tags/rel_0_3_beta/
38 add measures to implement XCHD arniml 7408d 08h /t48/tags/rel_0_3_beta/
37 add dump_compare support arniml 7408d 08h /t48/tags/rel_0_3_beta/
36 make calculation of expected value more readable arniml 7408d 09h /t48/tags/rel_0_3_beta/
35 initial check-in arniml 7411d 02h /t48/tags/rel_0_3_beta/
34 fix test wrt AC arniml 7414d 02h /t48/tags/rel_0_3_beta/
33 rename pX_limp to pX_low_imp arniml 7414d 02h /t48/tags/rel_0_3_beta/
32 rename pX_limp to pX_low_imp arniml 7414d 02h /t48/tags/rel_0_3_beta/
31 refer PROJECT_DIR variable arniml 7414d 03h /t48/tags/rel_0_3_beta/
30 connect prog_n_o arniml 7415d 01h /t48/tags/rel_0_3_beta/
29 take auxiliary carry from direct ALU connection arniml 7415d 01h /t48/tags/rel_0_3_beta/
28 update wiring for DA support arniml 7415d 01h /t48/tags/rel_0_3_beta/
27 implemented mnemonic DA arniml 7415d 01h /t48/tags/rel_0_3_beta/
26 support for DA instruction arniml 7415d 01h /t48/tags/rel_0_3_beta/
25 initial check-in arniml 7415d 01h /t48/tags/rel_0_3_beta/
24 connect control signal for Port 2 expander arniml 7415d 09h /t48/tags/rel_0_3_beta/
23 rework Port 2 expander handling arniml 7415d 09h /t48/tags/rel_0_3_beta/
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7415d 09h /t48/tags/rel_0_3_beta/
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A
arniml 7415d 09h /t48/tags/rel_0_3_beta/
20 move code for PROG out of if-branch for xtal3_s arniml 7415d 09h /t48/tags/rel_0_3_beta/
19 enhance simulation result string arniml 7416d 23h /t48/tags/rel_0_3_beta/
18 fix constant format arniml 7417d 00h /t48/tags/rel_0_3_beta/

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