URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] - Rev 100

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Rev	Log message	Author	Age	Path
100	reorder data_o generation	arniml	7366d 02h	/t48/tags/rel_0_3_beta/rtl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7366d 03h	/t48/tags/rel_0_3_beta/rtl/
92	work around bug in Quartus II 4.0	arniml	7367d 01h	/t48/tags/rel_0_3_beta/rtl/
91	fix edge detector bug for counter	arniml	7367d 01h	/t48/tags/rel_0_3_beta/rtl/
86	update notice about expander port instructions	arniml	7382d 05h	/t48/tags/rel_0_3_beta/rtl/
78	adjust external timing of BUS	arniml	7388d 00h	/t48/tags/rel_0_3_beta/rtl/
77	move from std_logic_arith to numeric_std	arniml	7388d 17h	/t48/tags/rel_0_3_beta/rtl/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7389d 05h	/t48/tags/rel_0_3_beta/rtl/
72	removed superfluous signal from sensitivity list	arniml	7389d 05h	/t48/tags/rel_0_3_beta/rtl/
66	add temporary workaround for GHDL 0.11	arniml	7394d 22h	/t48/tags/rel_0_3_beta/rtl/
65	clean up sensitivity list	arniml	7394d 22h	/t48/tags/rel_0_3_beta/rtl/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7394d 22h	/t48/tags/rel_0_3_beta/rtl/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7394d 22h	/t48/tags/rel_0_3_beta/rtl/
62	initial check-in	arniml	7394d 22h	/t48/tags/rel_0_3_beta/rtl/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7397d 18h	/t48/tags/rel_0_3_beta/rtl/
59	increment prescaler with MSTATE4	arniml	7397d 19h	/t48/tags/rel_0_3_beta/rtl/
54	- add tb_istrobe_s	arniml	7398d 20h	/t48/tags/rel_0_3_beta/rtl/
53	make istrobe visible through testbench package	arniml	7398d 20h	/t48/tags/rel_0_3_beta/rtl/
45	remove unused signals	arniml	7405d 18h	/t48/tags/rel_0_3_beta/rtl/
44	default assignment for aux_carry_o	arniml	7405d 20h	/t48/tags/rel_0_3_beta/rtl/
43	fix sensitivity list	arniml	7406d 20h	/t48/tags/rel_0_3_beta/rtl/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7406d 22h	/t48/tags/rel_0_3_beta/rtl/
38	add measures to implement XCHD	arniml	7409d 02h	/t48/tags/rel_0_3_beta/rtl/
37	add dump_compare support	arniml	7409d 02h	/t48/tags/rel_0_3_beta/rtl/
32	rename pX_limp to pX_low_imp	arniml	7414d 21h	/t48/tags/rel_0_3_beta/rtl/
29	take auxiliary carry from direct ALU connection	arniml	7415d 19h	/t48/tags/rel_0_3_beta/rtl/
28	update wiring for DA support	arniml	7415d 19h	/t48/tags/rel_0_3_beta/rtl/
27	implemented mnemonic DA	arniml	7415d 19h	/t48/tags/rel_0_3_beta/rtl/
26	support for DA instruction	arniml	7415d 19h	/t48/tags/rel_0_3_beta/rtl/
24	connect control signal for Port 2 expander	arniml	7416d 03h	/t48/tags/rel_0_3_beta/rtl/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] - Rev 100

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