OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_4_beta/] [rtl/] - Rev 129

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
129 cleanup copyright notice arniml 7331d 08h /t48/tags/rel_0_4_beta/rtl/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7338d 12h /t48/tags/rel_0_4_beta/rtl/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7342d 03h /t48/tags/rel_0_4_beta/rtl/
119 add int_in_progress_o to entity of int module arniml 7342d 04h /t48/tags/rel_0_4_beta/rtl/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7383d 03h /t48/tags/rel_0_4_beta/rtl/
107 tie EA to '1' arniml 7383d 03h /t48/tags/rel_0_4_beta/rtl/
106 clean-up use of ea_i arniml 7383d 03h /t48/tags/rel_0_4_beta/rtl/
101 assert p2_read_p2_o when expander port is read arniml 7386d 10h /t48/tags/rel_0_4_beta/rtl/
100 reorder data_o generation arniml 7386d 10h /t48/tags/rel_0_4_beta/rtl/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7386d 11h /t48/tags/rel_0_4_beta/rtl/
92 work around bug in Quartus II 4.0 arniml 7387d 09h /t48/tags/rel_0_4_beta/rtl/
91 fix edge detector bug for counter arniml 7387d 09h /t48/tags/rel_0_4_beta/rtl/
86 update notice about expander port instructions arniml 7402d 13h /t48/tags/rel_0_4_beta/rtl/
78 adjust external timing of BUS arniml 7408d 08h /t48/tags/rel_0_4_beta/rtl/
77 move from std_logic_arith to numeric_std arniml 7409d 01h /t48/tags/rel_0_4_beta/rtl/
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7409d 13h /t48/tags/rel_0_4_beta/rtl/
72 removed superfluous signal from sensitivity list arniml 7409d 13h /t48/tags/rel_0_4_beta/rtl/
66 add temporary workaround for GHDL 0.11 arniml 7415d 06h /t48/tags/rel_0_4_beta/rtl/
65 clean up sensitivity list arniml 7415d 06h /t48/tags/rel_0_4_beta/rtl/
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions		 arniml 7415d 06h /t48/tags/rel_0_4_beta/rtl/
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset		 arniml 7415d 06h /t48/tags/rel_0_4_beta/rtl/
62 initial check-in arniml 7415d 06h /t48/tags/rel_0_4_beta/rtl/
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls		 arniml 7418d 03h /t48/tags/rel_0_4_beta/rtl/
59 increment prescaler with MSTATE4 arniml 7418d 03h /t48/tags/rel_0_4_beta/rtl/
54 - add tb_istrobe_s arniml 7419d 04h /t48/tags/rel_0_4_beta/rtl/
53 make istrobe visible through testbench package arniml 7419d 04h /t48/tags/rel_0_4_beta/rtl/
45 remove unused signals arniml 7426d 03h /t48/tags/rel_0_4_beta/rtl/
44 default assignment for aux_carry_o arniml 7426d 04h /t48/tags/rel_0_4_beta/rtl/
43 fix sensitivity list arniml 7427d 04h /t48/tags/rel_0_4_beta/rtl/
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7427d 07h /t48/tags/rel_0_4_beta/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.