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[/] [t48/] [tags/] [rel_0_4_beta/] [rtl/] - Rev 329

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Rev Log message Author Age Path
292 New directory structure. root 5601d 22h /t48/tags/rel_0_4_beta/rtl/
254 This commit was manufactured by cvs2svn to create tag 'rel_0_4_beta'. 6572d 06h /t48/tags/rel_0_4_beta/rtl/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7242d 07h /t48/tags/rel_0_4_beta/rtl/
129 cleanup copyright notice arniml 7304d 15h /t48/tags/rel_0_4_beta/rtl/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7311d 18h /t48/tags/rel_0_4_beta/rtl/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7315d 10h /t48/tags/rel_0_4_beta/rtl/
119 add int_in_progress_o to entity of int module arniml 7315d 10h /t48/tags/rel_0_4_beta/rtl/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7356d 09h /t48/tags/rel_0_4_beta/rtl/
107 tie EA to '1' arniml 7356d 09h /t48/tags/rel_0_4_beta/rtl/
106 clean-up use of ea_i arniml 7356d 10h /t48/tags/rel_0_4_beta/rtl/
101 assert p2_read_p2_o when expander port is read arniml 7359d 17h /t48/tags/rel_0_4_beta/rtl/
100 reorder data_o generation arniml 7359d 17h /t48/tags/rel_0_4_beta/rtl/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7359d 18h /t48/tags/rel_0_4_beta/rtl/
92 work around bug in Quartus II 4.0 arniml 7360d 16h /t48/tags/rel_0_4_beta/rtl/
91 fix edge detector bug for counter arniml 7360d 16h /t48/tags/rel_0_4_beta/rtl/
86 update notice about expander port instructions arniml 7375d 19h /t48/tags/rel_0_4_beta/rtl/
78 adjust external timing of BUS arniml 7381d 15h /t48/tags/rel_0_4_beta/rtl/
77 move from std_logic_arith to numeric_std arniml 7382d 08h /t48/tags/rel_0_4_beta/rtl/
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7382d 20h /t48/tags/rel_0_4_beta/rtl/
72 removed superfluous signal from sensitivity list arniml 7382d 20h /t48/tags/rel_0_4_beta/rtl/
66 add temporary workaround for GHDL 0.11 arniml 7388d 12h /t48/tags/rel_0_4_beta/rtl/
65 clean up sensitivity list arniml 7388d 12h /t48/tags/rel_0_4_beta/rtl/
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions		 arniml 7388d 12h /t48/tags/rel_0_4_beta/rtl/
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset		 arniml 7388d 12h /t48/tags/rel_0_4_beta/rtl/
62 initial check-in arniml 7388d 13h /t48/tags/rel_0_4_beta/rtl/
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls		 arniml 7391d 09h /t48/tags/rel_0_4_beta/rtl/
59 increment prescaler with MSTATE4 arniml 7391d 09h /t48/tags/rel_0_4_beta/rtl/
54 - add tb_istrobe_s arniml 7392d 10h /t48/tags/rel_0_4_beta/rtl/
53 make istrobe visible through testbench package arniml 7392d 10h /t48/tags/rel_0_4_beta/rtl/
45 remove unused signals arniml 7399d 09h /t48/tags/rel_0_4_beta/rtl/

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