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[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 103

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103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7396d 15h /t48/tags/rel_0_5_beta/
102 update for changes in address space of external memory arniml 7396d 15h /t48/tags/rel_0_5_beta/
101 assert p2_read_p2_o when expander port is read arniml 7396d 15h /t48/tags/rel_0_5_beta/
100 reorder data_o generation arniml 7396d 16h /t48/tags/rel_0_5_beta/
99 initial check-in arniml 7396d 16h /t48/tags/rel_0_5_beta/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7396d 16h /t48/tags/rel_0_5_beta/
97 initial check-in arniml 7396d 16h /t48/tags/rel_0_5_beta/
96 select dedicated directorie(s) for regression arniml 7397d 14h /t48/tags/rel_0_5_beta/
95 check counter inactivity arniml 7397d 14h /t48/tags/rel_0_5_beta/
94 initial check-in arniml 7397d 14h /t48/tags/rel_0_5_beta/
93 add support for line coverage evaluation with gcov arniml 7397d 15h /t48/tags/rel_0_5_beta/
92 work around bug in Quartus II 4.0 arniml 7397d 15h /t48/tags/rel_0_5_beta/
91 fix edge detector bug for counter arniml 7397d 15h /t48/tags/rel_0_5_beta/
90 intial check-in arniml 7397d 15h /t48/tags/rel_0_5_beta/
89 initial check-in arniml 7411d 11h /t48/tags/rel_0_5_beta/
88 allow memory bank switching during interrupts arniml 7412d 13h /t48/tags/rel_0_5_beta/
87 abort gracfullt if memory bank switching does not work arniml 7412d 13h /t48/tags/rel_0_5_beta/
86 update notice about expander port instructions arniml 7412d 18h /t48/tags/rel_0_5_beta/
85 initial check-in arniml 7412d 18h /t48/tags/rel_0_5_beta/
84 add if_timing module arniml 7418d 09h /t48/tags/rel_0_5_beta/
83 connect if_timing to P2 output of T48 arniml 7418d 09h /t48/tags/rel_0_5_beta/
82 check expander timings arniml 7418d 09h /t48/tags/rel_0_5_beta/
81 initial check-in arniml 7418d 14h /t48/tags/rel_0_5_beta/
80 added if_timing arniml 7418d 14h /t48/tags/rel_0_5_beta/
79 add if_timing module arniml 7418d 14h /t48/tags/rel_0_5_beta/
78 adjust external timing of BUS arniml 7418d 14h /t48/tags/rel_0_5_beta/
77 move from std_logic_arith to numeric_std arniml 7419d 06h /t48/tags/rel_0_5_beta/
76 initial check-in arniml 7419d 10h /t48/tags/rel_0_5_beta/
75 remove obsolete design unit arniml 7419d 10h /t48/tags/rel_0_5_beta/
74 enhance pass/fail detection arniml 7419d 19h /t48/tags/rel_0_5_beta/

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