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[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 33

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Rev Log message Author Age Path
33 rename pX_limp to pX_low_imp arniml 7412d 02h /t48/tags/rel_0_5_beta/
32 rename pX_limp to pX_low_imp arniml 7412d 02h /t48/tags/rel_0_5_beta/
31 refer PROJECT_DIR variable arniml 7412d 02h /t48/tags/rel_0_5_beta/
30 connect prog_n_o arniml 7413d 00h /t48/tags/rel_0_5_beta/
29 take auxiliary carry from direct ALU connection arniml 7413d 00h /t48/tags/rel_0_5_beta/
28 update wiring for DA support arniml 7413d 00h /t48/tags/rel_0_5_beta/
27 implemented mnemonic DA arniml 7413d 00h /t48/tags/rel_0_5_beta/
26 support for DA instruction arniml 7413d 00h /t48/tags/rel_0_5_beta/
25 initial check-in arniml 7413d 00h /t48/tags/rel_0_5_beta/
24 connect control signal for Port 2 expander arniml 7413d 08h /t48/tags/rel_0_5_beta/
23 rework Port 2 expander handling arniml 7413d 08h /t48/tags/rel_0_5_beta/
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7413d 08h /t48/tags/rel_0_5_beta/
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A		 arniml 7413d 08h /t48/tags/rel_0_5_beta/
20 move code for PROG out of if-branch for xtal3_s arniml 7413d 08h /t48/tags/rel_0_5_beta/
19 enhance simulation result string arniml 7414d 23h /t48/tags/rel_0_5_beta/
18 fix constant format arniml 7414d 23h /t48/tags/rel_0_5_beta/
17 fix test arniml 7414d 23h /t48/tags/rel_0_5_beta/
16 fix header arniml 7414d 23h /t48/tags/rel_0_5_beta/
15 initial check-in arniml 7415d 22h /t48/tags/rel_0_5_beta/
14 initial check-in arniml 7415d 23h /t48/tags/rel_0_5_beta/
12 Imported sources arniml 7415d 23h /t48/tags/rel_0_5_beta/
11 add description arniml 7415d 23h /t48/tags/rel_0_5_beta/
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7416d 22h /t48/tags/rel_0_5_beta/
9 initial check-in arniml 7416d 22h /t48/tags/rel_0_5_beta/
8 initial check-in arniml 7417d 00h /t48/tags/rel_0_5_beta/
7 initial check-in arniml 7417d 00h /t48/tags/rel_0_5_beta/
6 moved to system directory arniml 7417d 00h /t48/tags/rel_0_5_beta/
5 initial check-in arniml 7418d 00h /t48/tags/rel_0_5_beta/
4 initial check-in arniml 7418d 00h /t48/tags/rel_0_5_beta/
3 bummer arniml 7418d 00h /t48/tags/rel_0_5_beta/

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