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[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 121

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Rev Log message Author Age Path
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7338d 21h /t48/tags/rel_0_6_1_beta/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7338d 21h /t48/tags/rel_0_6_1_beta/
119 add int_in_progress_o to entity of int module arniml 7338d 21h /t48/tags/rel_0_6_1_beta/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7338d 21h /t48/tags/rel_0_6_1_beta/
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7339d 21h /t48/tags/rel_0_6_1_beta/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7367d 21h /t48/tags/rel_0_6_1_beta/
115 extend description arniml 7369d 02h /t48/tags/rel_0_6_1_beta/
114 initial check-in arniml 7372d 21h /t48/tags/rel_0_6_1_beta/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7379d 07h /t48/tags/rel_0_6_1_beta/
112 update tb_behav_c0 for new ROM layout arniml 7379d 07h /t48/tags/rel_0_6_1_beta/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7379d 07h /t48/tags/rel_0_6_1_beta/
110 exchange syn_rom for lpm_rom arniml 7379d 07h /t48/tags/rel_0_6_1_beta/
109 add new bug for release 0.1 BETA arniml 7379d 20h /t48/tags/rel_0_6_1_beta/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7379d 20h /t48/tags/rel_0_6_1_beta/
107 tie EA to '1' arniml 7379d 20h /t48/tags/rel_0_6_1_beta/
106 clean-up use of ea_i arniml 7379d 20h /t48/tags/rel_0_6_1_beta/
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7382d 06h /t48/tags/rel_0_6_1_beta/
104 add white_box directory to test suite arniml 7383d 03h /t48/tags/rel_0_6_1_beta/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7383d 03h /t48/tags/rel_0_6_1_beta/
102 update for changes in address space of external memory arniml 7383d 03h /t48/tags/rel_0_6_1_beta/
101 assert p2_read_p2_o when expander port is read arniml 7383d 03h /t48/tags/rel_0_6_1_beta/
100 reorder data_o generation arniml 7383d 03h /t48/tags/rel_0_6_1_beta/
99 initial check-in arniml 7383d 03h /t48/tags/rel_0_6_1_beta/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7383d 04h /t48/tags/rel_0_6_1_beta/
97 initial check-in arniml 7383d 04h /t48/tags/rel_0_6_1_beta/
96 select dedicated directorie(s) for regression arniml 7384d 02h /t48/tags/rel_0_6_1_beta/
95 check counter inactivity arniml 7384d 02h /t48/tags/rel_0_6_1_beta/
94 initial check-in arniml 7384d 02h /t48/tags/rel_0_6_1_beta/
93 add support for line coverage evaluation with gcov arniml 7384d 02h /t48/tags/rel_0_6_1_beta/
92 work around bug in Quartus II 4.0 arniml 7384d 02h /t48/tags/rel_0_6_1_beta/

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