| Rev |
Log message |
Author |
Age |
Path |
| 148 |
initial check-in |
arniml |
7162d 07h |
/t48/tags/rel_0_6_1_beta/ |
| 147 |
initial check-in for release 0.5 BETA |
arniml |
7198d 08h |
/t48/tags/rel_0_6_1_beta/ |
| 146 |
add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A |
arniml |
7199d 08h |
/t48/tags/rel_0_6_1_beta/ |
| 145 |
remove PROG and end of XTAL2, see comment for details |
arniml |
7199d 09h |
/t48/tags/rel_0_6_1_beta/ |
| 144 |
delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR' |
arniml |
7199d 09h |
/t48/tags/rel_0_6_1_beta/ |
| 143 |
Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle |
arniml |
7199d 10h |
/t48/tags/rel_0_6_1_beta/ |
| 142 |
deassert rd_q, wr_q and prog_q at end of XTAL3 |
arniml |
7199d 10h |
/t48/tags/rel_0_6_1_beta/ |
| 141 |
disable external memory to avoid conflicts with outl a, bus |
arniml |
7199d 10h |
/t48/tags/rel_0_6_1_beta/ |
| 140 |
remove tAW sanity check
conflicts with OUTL A, BUS |
arniml |
7199d 10h |
/t48/tags/rel_0_6_1_beta/ |
| 139 |
add bug
P1 constantly in push-pull mode in t8048 |
arniml |
7200d 21h |
/t48/tags/rel_0_6_1_beta/ |
| 138 |
Fix for:
P1 constantly in push-pull mode in t8048 |
arniml |
7200d 21h |
/t48/tags/rel_0_6_1_beta/ |
| 137 |
add link to COMPILE_LIST |
arniml |
7238d 09h |
/t48/tags/rel_0_6_1_beta/ |
| 136 |
initial check-in |
arniml |
7238d 09h |
/t48/tags/rel_0_6_1_beta/ |
| 135 |
add bug
PSENn Timing |
arniml |
7242d 20h |
/t48/tags/rel_0_6_1_beta/ |
| 134 |
Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR. |
arniml |
7243d 05h |
/t48/tags/rel_0_6_1_beta/ |
| 133 |
add checks for PSEN |
arniml |
7243d 05h |
/t48/tags/rel_0_6_1_beta/ |
| 132 |
stop simulation upon assertion error |
arniml |
7243d 05h |
/t48/tags/rel_0_6_1_beta/ |
| 131 |
update |
arniml |
7243d 05h |
/t48/tags/rel_0_6_1_beta/ |
| 130 |
initial check-in |
arniml |
7243d 05h |
/t48/tags/rel_0_6_1_beta/ |
| 129 |
cleanup copyright notice |
arniml |
7305d 13h |
/t48/tags/rel_0_6_1_beta/ |
| 128 |
counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered |
arniml |
7312d 17h |
/t48/tags/rel_0_6_1_beta/ |
| 127 |
+ log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge |
arniml |
7312d 18h |
/t48/tags/rel_0_6_1_beta/ |
| 126 |
+ specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell |
arniml |
7312d 18h |
/t48/tags/rel_0_6_1_beta/ |
| 125 |
exclude from dump compare |
arniml |
7312d 18h |
/t48/tags/rel_0_6_1_beta/ |
| 124 |
fix wrong handling of MB after return from interrupt |
arniml |
7313d 15h |
/t48/tags/rel_0_6_1_beta/ |
| 123 |
support hex file for external ROM |
arniml |
7313d 15h |
/t48/tags/rel_0_6_1_beta/ |
| 122 |
test MB after return from interrupt |
arniml |
7313d 15h |
/t48/tags/rel_0_6_1_beta/ |
| 121 |
update bug description for
Program Memory bank can be switched during interrupt |
arniml |
7316d 08h |
/t48/tags/rel_0_6_1_beta/ |
| 120 |
Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts |
arniml |
7316d 09h |
/t48/tags/rel_0_6_1_beta/ |
| 119 |
add int_in_progress_o to entity of int module |
arniml |
7316d 09h |
/t48/tags/rel_0_6_1_beta/ |
