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[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 217

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Rev Log message Author Age Path
217 update for release 0.6.1 beta arniml 6764d 16h /t48/tags/rel_0_6_1_beta/
216 assign clk_i to outclock arniml 6826d 16h /t48/tags/rel_0_6_1_beta/
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory		 arniml 6826d 16h /t48/tags/rel_0_6_1_beta/
214 fix sensitivity list arniml 6833d 17h /t48/tags/rel_0_6_1_beta/
213 properly drive P1 and P2 with low impedance markers arniml 6838d 13h /t48/tags/rel_0_6_1_beta/
212 add bug reports
"Problem when INT and JMP"
"P2 Port value restored after expander access"		 arniml 6838d 15h /t48/tags/rel_0_6_1_beta/
211 wire signals for P2 low impedance marker issue arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
210 entity changes for P2 low impedance marker issue arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
209 entity changes for P2 low impedance issue arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
208 wire signals for P2 low impeddance marker issue arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
207 entity changes for P2 low impedance trigger issue arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
202 fix address assignment arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
201 split low impedance markers for P2 arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6839d 15h /t48/tags/rel_0_6_1_beta/
199 initial check-in arniml 6839d 16h /t48/tags/rel_0_6_1_beta/
198 fix package dependencies arniml 6839d 20h /t48/tags/rel_0_6_1_beta/
197 preliminary version 0.3 arniml 6840d 23h /t48/tags/rel_0_6_1_beta/
196 update to version 0.3 arniml 6840d 23h /t48/tags/rel_0_6_1_beta/
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"		 arniml 6841d 03h /t48/tags/rel_0_6_1_beta/
194 initial check-in arniml 6841d 03h /t48/tags/rel_0_6_1_beta/
193 iManual arniml 6856d 05h /t48/tags/rel_0_6_1_beta/
192 update list for Wishbone toplevel arniml 6856d 16h /t48/tags/rel_0_6_1_beta/
191 preliminary version 0.2 arniml 6856d 19h /t48/tags/rel_0_6_1_beta/
190 finalize change log for release 0.6 beta arniml 6857d 13h /t48/tags/rel_0_6_1_beta/
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6888d 15h /t48/tags/rel_0_6_1_beta/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6888d 16h /t48/tags/rel_0_6_1_beta/

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