URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_0_6_1_beta/] [bench/] - Rev 292

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5679d 08h	/t48/tags/rel_0_6_1_beta/bench/
256	This commit was manufactured by cvs2svn to create tag 'rel_0_6_1_beta'.		6649d 16h	/t48/tags/rel_0_6_1_beta/bench/
202	fix address assignment	arniml	6903d 20h	/t48/tags/rel_0_6_1_beta/bench/
201	split low impedance markers for P2	arniml	6903d 20h	/t48/tags/rel_0_6_1_beta/bench/
200	add check for tCP: Port Control Setup to PROG'	arniml	6903d 20h	/t48/tags/rel_0_6_1_beta/bench/
183	fix missing assignment to outclock	arniml	6959d 00h	/t48/tags/rel_0_6_1_beta/bench/
160	add others to case statement	arniml	7236d 21h	/t48/tags/rel_0_6_1_beta/bench/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7275d 22h	/t48/tags/rel_0_6_1_beta/bench/
133	add checks for PSEN	arniml	7319d 17h	/t48/tags/rel_0_6_1_beta/bench/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7433d 06h	/t48/tags/rel_0_6_1_beta/bench/
110	exchange syn_rom for lpm_rom	arniml	7433d 06h	/t48/tags/rel_0_6_1_beta/bench/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7437d 03h	/t48/tags/rel_0_6_1_beta/bench/
83	connect if_timing to P2 output of T48	arniml	7458d 21h	/t48/tags/rel_0_6_1_beta/bench/
82	check expander timings	arniml	7458d 21h	/t48/tags/rel_0_6_1_beta/bench/
81	initial check-in	arniml	7459d 01h	/t48/tags/rel_0_6_1_beta/bench/
80	added if_timing	arniml	7459d 01h	/t48/tags/rel_0_6_1_beta/bench/
68	connect T0 and T1 to P1	arniml	7465d 22h	/t48/tags/rel_0_6_1_beta/bench/
67	initial check-in	arniml	7465d 22h	/t48/tags/rel_0_6_1_beta/bench/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7469d 20h	/t48/tags/rel_0_6_1_beta/bench/
33	rename pX_limp to pX_low_imp	arniml	7485d 22h	/t48/tags/rel_0_6_1_beta/bench/
30	connect prog_n_o	arniml	7486d 20h	/t48/tags/rel_0_6_1_beta/bench/
19	enhance simulation result string	arniml	7488d 19h	/t48/tags/rel_0_6_1_beta/bench/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7490d 18h	/t48/tags/rel_0_6_1_beta/bench/
8	initial check-in	arniml	7490d 20h	/t48/tags/rel_0_6_1_beta/bench/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [bench/] - Rev 292

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