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[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] - Rev 208

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208 wire signals for P2 low impeddance marker issue arniml 6832d 07h /t48/tags/rel_0_6_1_beta/rtl/
207 entity changes for P2 low impedance trigger issue arniml 6832d 07h /t48/tags/rel_0_6_1_beta/rtl/
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6832d 07h /t48/tags/rel_0_6_1_beta/rtl/
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6832d 07h /t48/tags/rel_0_6_1_beta/rtl/
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6832d 07h /t48/tags/rel_0_6_1_beta/rtl/
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6832d 07h /t48/tags/rel_0_6_1_beta/rtl/
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"		 arniml 6833d 18h /t48/tags/rel_0_6_1_beta/rtl/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6881d 07h /t48/tags/rel_0_6_1_beta/rtl/
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6881d 07h /t48/tags/rel_0_6_1_beta/rtl/
183 fix missing assignment to outclock arniml 6887d 11h /t48/tags/rel_0_6_1_beta/rtl/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6975d 18h /t48/tags/rel_0_6_1_beta/rtl/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6975d 18h /t48/tags/rel_0_6_1_beta/rtl/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6977d 06h /t48/tags/rel_0_6_1_beta/rtl/
177 Implement db_dir_o glitch-safe arniml 6977d 06h /t48/tags/rel_0_6_1_beta/rtl/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6977d 06h /t48/tags/rel_0_6_1_beta/rtl/
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6978d 09h /t48/tags/rel_0_6_1_beta/rtl/
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7007d 06h /t48/tags/rel_0_6_1_beta/rtl/
171 remove obsolete output stack_high_o arniml 7008d 06h /t48/tags/rel_0_6_1_beta/rtl/
169 initial check-in arniml 7009d 18h /t48/tags/rel_0_6_1_beta/rtl/
168 change address range of wb_master arniml 7009d 18h /t48/tags/rel_0_6_1_beta/rtl/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7009d 18h /t48/tags/rel_0_6_1_beta/rtl/
166 assign default for state_s arniml 7011d 09h /t48/tags/rel_0_6_1_beta/rtl/
165 add component wb_master.vhd arniml 7012d 08h /t48/tags/rel_0_6_1_beta/rtl/
164 initial check-in arniml 7012d 08h /t48/tags/rel_0_6_1_beta/rtl/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7013d 08h /t48/tags/rel_0_6_1_beta/rtl/
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7044d 12h /t48/tags/rel_0_6_1_beta/rtl/
157 removed obsolete constant arniml 7165d 09h /t48/tags/rel_0_6_1_beta/rtl/
156 added hierarchy t8039_notri arniml 7165d 09h /t48/tags/rel_0_6_1_beta/rtl/
155 initial check-in arniml 7165d 09h /t48/tags/rel_0_6_1_beta/rtl/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7166d 06h /t48/tags/rel_0_6_1_beta/rtl/

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