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[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] [vhdl/] - Rev 345

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292 New directory structure. root 5607d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
256 This commit was manufactured by cvs2svn to create tag 'rel_0_6_1_beta'. 6577d 20h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
216 assign clk_i to outclock arniml 6819d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory		 arniml 6819d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
214 fix sensitivity list arniml 6826d 02h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
213 properly drive P1 and P2 with low impedance markers arniml 6830d 21h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
211 wire signals for P2 low impedance marker issue arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
210 entity changes for P2 low impedance marker issue arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
209 entity changes for P2 low impedance issue arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
208 wire signals for P2 low impeddance marker issue arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
207 entity changes for P2 low impedance trigger issue arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6832d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"		 arniml 6833d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6881d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6881d 00h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
183 fix missing assignment to outclock arniml 6887d 04h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6975d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6975d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6976d 23h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
177 Implement db_dir_o glitch-safe arniml 6976d 23h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6976d 23h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6978d 02h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7006d 23h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
171 remove obsolete output stack_high_o arniml 7007d 23h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
169 initial check-in arniml 7009d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
168 change address range of wb_master arniml 7009d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7009d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/

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