URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [sw/] [verif/] - Rev 329

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5701d 16h	/t48/tags/rel_0_6_1_beta/sw/verif/
256	This commit was manufactured by cvs2svn to create tag 'rel_0_6_1_beta'.		6672d 01h	/t48/tags/rel_0_6_1_beta/sw/verif/
199	initial check-in	arniml	6926d 05h	/t48/tags/rel_0_6_1_beta/sw/verif/
194	initial check-in	arniml	6927d 16h	/t48/tags/rel_0_6_1_beta/sw/verif/
185	initial check-in	arniml	6981d 04h	/t48/tags/rel_0_6_1_beta/sw/verif/
184	initial check-in	arniml	6981d 05h	/t48/tags/rel_0_6_1_beta/sw/verif/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7072d 07h	/t48/tags/rel_0_6_1_beta/sw/verif/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7298d 06h	/t48/tags/rel_0_6_1_beta/sw/verif/
131	update	arniml	7342d 01h	/t48/tags/rel_0_6_1_beta/sw/verif/
130	initial check-in	arniml	7342d 01h	/t48/tags/rel_0_6_1_beta/sw/verif/
125	exclude from dump compare	arniml	7411d 14h	/t48/tags/rel_0_6_1_beta/sw/verif/
122	test MB after return from interrupt	arniml	7412d 11h	/t48/tags/rel_0_6_1_beta/sw/verif/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7415d 05h	/t48/tags/rel_0_6_1_beta/sw/verif/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7455d 14h	/t48/tags/rel_0_6_1_beta/sw/verif/
102	update for changes in address space of external memory	arniml	7459d 11h	/t48/tags/rel_0_6_1_beta/sw/verif/
99	initial check-in	arniml	7459d 11h	/t48/tags/rel_0_6_1_beta/sw/verif/
97	initial check-in	arniml	7459d 12h	/t48/tags/rel_0_6_1_beta/sw/verif/
95	check counter inactivity	arniml	7460d 09h	/t48/tags/rel_0_6_1_beta/sw/verif/
94	initial check-in	arniml	7460d 09h	/t48/tags/rel_0_6_1_beta/sw/verif/
90	intial check-in	arniml	7460d 10h	/t48/tags/rel_0_6_1_beta/sw/verif/
89	initial check-in	arniml	7474d 07h	/t48/tags/rel_0_6_1_beta/sw/verif/
87	abort gracfullt if memory bank switching does not work	arniml	7475d 08h	/t48/tags/rel_0_6_1_beta/sw/verif/
85	initial check-in	arniml	7475d 14h	/t48/tags/rel_0_6_1_beta/sw/verif/
57	abort if no interrupt occurs	arniml	7491d 04h	/t48/tags/rel_0_6_1_beta/sw/verif/
46	fix test	arniml	7499d 04h	/t48/tags/rel_0_6_1_beta/sw/verif/
42	change test values that match better to the test case	arniml	7500d 08h	/t48/tags/rel_0_6_1_beta/sw/verif/
39	initial check-in	arniml	7502d 11h	/t48/tags/rel_0_6_1_beta/sw/verif/
36	make calculation of expected value more readable	arniml	7502d 12h	/t48/tags/rel_0_6_1_beta/sw/verif/
34	fix test wrt AC	arniml	7508d 06h	/t48/tags/rel_0_6_1_beta/sw/verif/
25	initial check-in	arniml	7509d 05h	/t48/tags/rel_0_6_1_beta/sw/verif/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [sw/] [verif/] - Rev 329

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