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[/] [t48/] [tags/] [rel_0_6__beta/] - Rev 301

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5571d 11h	/t48/tags/rel_0_6__beta/
257	This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'.		6541d 20h	/tags/rel_0_6__beta/
193	iManual	arniml	6812d 13h	/trunk/
192	update list for Wishbone toplevel	arniml	6813d 00h	/trunk/
191	preliminary version 0.2	arniml	6813d 03h	/trunk/
190	finalize change log for release 0.6 beta	arniml	6813d 22h	/trunk/
189	add bug report "Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"	arniml	6844d 23h	/trunk/
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6845d 00h	/trunk/
187	Fix bug reports: "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" int_in_progress_o was active one cycle before int_pending_o is asserted. this confused the mb multiplexer which determines the state of the memory bank selection flag	arniml	6845d 00h	/trunk/
186	update to version 0.2	arniml	6846d 01h	/trunk/
185	initial check-in	arniml	6850d 23h	/trunk/
184	initial check-in	arniml	6851d 01h	/trunk/
183	fix missing assignment to outclock	arniml	6851d 03h	/trunk/
182	intermediate version	arniml	6931d 02h	/trunk/
181	fix typo	arniml	6931d 05h	/trunk/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6939d 11h	/trunk/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6939d 11h	/trunk/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6940d 23h	/trunk/
177	Implement db_dir_o glitch-safe	arniml	6940d 23h	/trunk/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6940d 23h	/trunk/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	6942d 02h	/trunk/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6942d 02h	/trunk/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6942d 02h	/trunk/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	6970d 22h	/trunk/
171	remove obsolete output stack_high_o	arniml	6971d 22h	/trunk/
170	intermediate update	arniml	6973d 05h	/trunk/
169	initial check-in	arniml	6973d 10h	/trunk/
168	change address range of wb_master	arniml	6973d 10h	/trunk/
167	simplify address range: - configuration range - Wishbone range	arniml	6973d 10h	/trunk/
166	assign default for state_s	arniml	6975d 02h	/trunk/

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[/] [t48/] [tags/] [rel_0_6__beta/] - Rev 301

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