OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 136

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
136 initial check-in arniml 7271d 22h /t48/tags/rel_0_6_beta/
135 add bug
PSENn Timing		 arniml 7276d 09h /t48/tags/rel_0_6_beta/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7276d 19h /t48/tags/rel_0_6_beta/
133 add checks for PSEN arniml 7276d 19h /t48/tags/rel_0_6_beta/
132 stop simulation upon assertion error arniml 7276d 19h /t48/tags/rel_0_6_beta/
131 update arniml 7276d 19h /t48/tags/rel_0_6_beta/
130 initial check-in arniml 7276d 19h /t48/tags/rel_0_6_beta/
129 cleanup copyright notice arniml 7339d 02h /t48/tags/rel_0_6_beta/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7346d 06h /t48/tags/rel_0_6_beta/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7346d 07h /t48/tags/rel_0_6_beta/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7346d 07h /t48/tags/rel_0_6_beta/
125 exclude from dump compare arniml 7346d 07h /t48/tags/rel_0_6_beta/
124 fix wrong handling of MB after return from interrupt arniml 7347d 05h /t48/tags/rel_0_6_beta/
123 support hex file for external ROM arniml 7347d 05h /t48/tags/rel_0_6_beta/
122 test MB after return from interrupt arniml 7347d 05h /t48/tags/rel_0_6_beta/
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7349d 22h /t48/tags/rel_0_6_beta/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7349d 22h /t48/tags/rel_0_6_beta/
119 add int_in_progress_o to entity of int module arniml 7349d 22h /t48/tags/rel_0_6_beta/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7349d 22h /t48/tags/rel_0_6_beta/
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7350d 23h /t48/tags/rel_0_6_beta/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7378d 23h /t48/tags/rel_0_6_beta/
115 extend description arniml 7380d 03h /t48/tags/rel_0_6_beta/
114 initial check-in arniml 7383d 23h /t48/tags/rel_0_6_beta/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7390d 08h /t48/tags/rel_0_6_beta/
112 update tb_behav_c0 for new ROM layout arniml 7390d 08h /t48/tags/rel_0_6_beta/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7390d 08h /t48/tags/rel_0_6_beta/
110 exchange syn_rom for lpm_rom arniml 7390d 08h /t48/tags/rel_0_6_beta/
109 add new bug for release 0.1 BETA arniml 7390d 21h /t48/tags/rel_0_6_beta/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7390d 21h /t48/tags/rel_0_6_beta/
107 tie EA to '1' arniml 7390d 21h /t48/tags/rel_0_6_beta/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.